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1.发明申请EDDY CURRENT LOSS MEASURING SENSOR, THICKNESS MEASURING SYSTEM, THICKNESS MEASURING METHOD, AND RECORDED MEDIUM 有权EDDY电流损耗测量传感器，厚度测量系统，厚度测量方法和记录介质公开(公告)号：US20030067298A1
公开(公告)日：2003-04-10
申请号：US09817147
申请日：2001-03-27
IPC分类号： G01B007/06 , G01R033/12
CPC分类号： G01B11/0608 , G01B7/105
摘要： A thickness measuring system comprises: an eddy current loss measuring sensor having an exciting coil for receiving a high frequency current to excite a high frequency magnetic field to excite an eddy current in a conductive film, and a receiving coil for outputting the high frequency current which is influenced by an eddy current loss caused by the eddy current; an impedance analyzer for measuring the variation in impedance of the eddy current loss measuring sensor, the variation in current value of the high frequency current or the variation in phase of the high frequency current on the basis of the high frequency current outputted from the receiving coil; an optical displacement sensor for measuring the distance between the conductive film and the eddy current loss measuring sensor; and a control computer including a thickness calculating part for calculating the thickness of the conductive film on the basis of various measured results of the impedance analyzer and optical displacement sensor, and the eddy current loss measuring sensor further has a ferrite member surrounding the exciting coil and the ferrite member has an opening in the bottom surface portion thereof for allowing the exciting coil to be exposed.
摘要翻译： 一种厚度测量系统，包括：具有用于接收高频电流以激发高频磁场以激励导电膜中的涡流的激励线圈的涡流损耗测量传感器，以及用于输出高频电流的接收线圈， 受涡流引起的涡流损耗的影响; 阻抗分析器，用于根据从接收线圈输出的高频电流来测量涡流损耗测量传感器的阻抗变化，高频电流的电流值的变化或高频电流的相位变化 ; 用于测量导电膜和涡流损耗测量传感器之间的距离的光学位移传感器; 以及控制计算机，其包括基于阻抗分析器和光学位移传感器的各种测量结果计算导电膜的厚度的厚度计算部分，并且涡流损耗测量传感器还具有围绕励磁线圈的铁氧体部件， 铁氧体部件在其底面部分具有允许激励线圈露出的开口。
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公开(公告)号：US20010038147A1
公开(公告)日：2001-11-08
申请号：US09903992
申请日：2001-07-13
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L021/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
摘要翻译： 一种半导体器件的制造方法，其特征在于，在形成于半导体衬底上的第一绝缘膜上形成沟槽，在所述沟槽中形成下层配线的工序，在所述半导体衬底上形成至少一层导体层， 在导电层上形成至少一层薄膜层的步骤，通过图案化薄膜形成硬掩模的步骤，通过使用硬掩模作为蚀刻掩模蚀刻导电层的步骤，以及形成 导电柱状结构，其上表面被硬掩模覆盖在下层布线上;在半导体基板上形成第二绝缘膜以使柱状结构被埋设的步骤，形成 至少暴露硬掩模的布线沟槽以及在去除硬掩模之后将导体埋入布线沟槽中的步骤，以及在布线沟槽中形成上层布线。
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公开(公告)号：US20010033894A1
公开(公告)日：2001-10-25
申请号：US09805034
申请日：2001-03-14
发明人： Hiroko Nakamura , Hisashi Kaneko , Tetsuo Matsuda
IPC分类号： B05D003/12 , B05C013/02
CPC分类号： H01L21/6715 , B05C9/02 , B05D1/286
摘要： After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.
摘要翻译： 在通过将液体试剂供应到板状显影剂载体上形成薄液剂剂膜之后，该液体试剂膜和基材的表面相对。 通过使基板下降并使其靠近液体试剂膜，或者通过使基板朝向液体试剂膜弯曲而使液体试剂膜和基板彼此接触。 然后，使基板与液体试剂膜平行，并且供给液体试剂，使得液体试剂膜的接触面积通过液体试剂膜和基底之间的界面张力在整个表面上扩散。 由于可以在基板的下方均匀地形成薄的液体试剂膜，因此能够以小的消耗量进行处理。 此外，可以在不保持空气的情况下将液体试剂供给到基材。
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公开(公告)号：US20010013617A1
公开(公告)日：2001-08-16
申请号：US09767724
申请日：2001-01-24
IPC分类号： H01L027/108 , H01L029/76 , H01L021/44 , H01L021/4763
CPC分类号： H01L21/76849 , H01L21/76819 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。
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公开(公告)号：US20030214010A1
公开(公告)日：2003-11-20
申请号：US10424856
申请日：2003-04-29
IPC分类号： H01L029/00
CPC分类号： H01L21/76849 , H01L21/76819 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L23/53242 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。
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公开(公告)号：US20040259297A1
公开(公告)日：2004-12-23
申请号：US10893948
申请日：2004-07-20
发明人： Seiji Inumiya , Katsuhiko Hieda , Tetsuo Matsuda , Yoshio Ozawa
IPC分类号： H01L021/338 , H01L021/00 , H01L021/84 , H01L021/336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
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公开(公告)号：US20040005774A1
公开(公告)日：2004-01-08
申请号：US10600568
申请日：2003-06-23
发明人： Hiroshi Toyoda , Hiroyuki Yano , Gaku Minamihaba , Dai Fukushima , Tetsuo Matsuda , Hisashi Kaneko
IPC分类号： H01L021/4763
CPC分类号： H01L21/76846 , H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (nullremoval rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (nullremoval rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
摘要翻译： 形成盖膜的方法包括以R1的选择性（=绝缘膜的除去速率/绝缘膜的去除速率）进行抛光操作的第一抛光步骤，以及以选择性进行抛光操作的第二抛光步骤 的R2（=盖膜的去除率/绝缘膜的去除率）。 通过使用条件为R1> R2的浆料进行每次研磨操作。 通过以不同的选择性进行抛光操作，形成了帽膜没有诸如凹陷的盖膜和残留帽膜之间的问题。 因此，可以提供具有优异RC特性的半导体器件。
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公开(公告)号：US20040203221A1
公开(公告)日：2004-10-14
申请号：US10835319
申请日：2004-04-30
发明人： Tetsuo Matsuda , Hiroshi Toyoda , Hisashi Kaneko
IPC分类号： H01L021/4763
CPC分类号： H01L21/76874 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/405 , C23C18/54 , C23C28/00 , C25D7/123 , H01L21/2855 , H01L21/288 , H01L21/76867 , H01L21/76868 , H01L21/76873 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
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公开(公告)号：US20020117698A1
公开(公告)日：2002-08-29
申请号：US10132255
申请日：2002-04-26
发明人： Seiji Inumiya , Katsuhiko Hieda , Tetsuo Matsuda , Yoshio Ozawa
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119 , H01L029/40 , H01L021/4763 , H01L021/336 , H01L029/792 , H01L023/48 , H01L021/3205 , H01L023/52
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4983 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/6659
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。
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公开(公告)号：US20020096435A1
公开(公告)日：2002-07-25
申请号：US10107425
申请日：2002-03-28
发明人： Tetsuo Matsuda , Hisashi Kaneko , Katsuya Okumura
IPC分类号： C25D005/06 , C25D017/00 , C25B009/00 , C25B015/00 , C25D021/12 , B23H007/04
CPC分类号： C25D5/16 , C25D5/02 , C25D5/06 , C25D7/123 , C25D17/001 , C25D17/12 , H01L21/2885 , H01L21/76877 , H05K3/423
摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.
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