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    Semiconductor device and method of manufacturing the same
    1.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20030214010A1

    公开(公告)日：2003-11-20

    申请号：US10424856

    申请日：2003-04-29

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    IPC分类号： H01L029/00

    CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

    Semiconductor device and method of manufacturing the same
    2.
    发明申请
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20010013617A1

    公开(公告)日：2001-08-16

    申请号：US09767724

    申请日：2001-01-24

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

    IPC分类号： H01L027/108 ,  H01L029/76 ,  H01L021/44 ,  H01L021/4763

    CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

    Electronic device manufacturing method
    4.
    发明申请
    Electronic device manufacturing method 失效
    电子元件制造方法

    公开(公告)号：US20020050459A1

    公开(公告)日：2002-05-02

    申请号：US09985051

    申请日：2001-11-01

    申请人： Kabushiki Kaisha Toshiba

    发明人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

    IPC分类号： C25D005/02 ,  C23C028/02

    CPC分类号： H01L21/76874 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/405 ,  C23C18/54 ,  C23C28/00 ,  C25D7/123 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

    摘要翻译： 一种电子器件制造方法，包括在基板上形成绝缘膜，形成包含所述绝缘膜中的互连槽和孔中的至少一个的待填充区域，形成含有催化剂金属的第一导电膜，其加速 化学镀，以便将要填充区域的内表面排列，通过化学镀在第一导电膜上形成第二导电膜，以便将被填充区域的内表面经由 第一导电膜，并且通过电镀在第二导电膜上形成第三导电膜，以便经由第一导电膜和第二导电膜填充待填充区域。

    Method of manufacturing semiconductor device and semiconductor device
    6.
    发明申请
    Method of manufacturing semiconductor device and semiconductor device 失效
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20040005774A1

    公开(公告)日：2004-01-08

    申请号：US10600568

    申请日：2003-06-23

    申请人： Kabushiki Kaisha Toshiba

    发明人： Hiroshi Toyoda ,  Hiroyuki Yano ,  Gaku Minamihaba ,  Dai Fukushima ,  Tetsuo Matsuda ,  Hisashi Kaneko

    IPC分类号： H01L021/4763

    CPC分类号： H01L21/76846 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (nullremoval rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (nullremoval rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.

    摘要翻译： 形成盖膜的方法包括以R1的选择性（=绝缘膜的除去速率/绝缘膜的去除速率）进行抛光操作的第一抛光步骤，以及以选择性进行抛光操作的第二抛光步骤 的R2（=盖膜的去除率/绝缘膜的去除率）。 通过使用条件为R1> R2的浆料进行每次研磨操作。 通过以不同的选择性进行抛光操作，形成了帽膜没有诸如凹陷的盖膜和残留帽膜之间的问题。 因此，可以提供具有优异RC特性的半导体器件。