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    Circuitized substrate with low loss capacitive material and method of making same
    1.
    发明授权
    Circuitized substrate with low loss capacitive material and method of making same 有权
    具有低损耗电容性材料的电路化基板及其制造方法

    公开(公告)号：US08446707B1

    公开(公告)日：2013-05-21

    申请号：US13269770

    申请日：2011-10-10

    申请人： Rabindra N. Das ,  Konstantinos I. Papathomas ,  Voya R. Markovich ,  James J. McNamara

    发明人： Rabindra N. Das ,  Konstantinos I. Papathomas ,  Voya R. Markovich ,  James J. McNamara

    IPC分类号： H01G4/06

    CPC分类号： H01G4/33 ,  H01G7/06 ,  H05K1/0231 ,  H05K3/429 ,  H05K3/4602

    摘要： A low loss capacitance and low loss insulating dielectric material consisting of a thermosetting resin, thermoplastic resin, a cross-linker, and containing a quantity of ferroelectric ceramic nano-particles of barium titanate within. The combined low loss insulating dielectric layer and a low loss capacitive layer resulting from the material allows one continuous layer that can form internal capacitors and permit the modifying the dielectric thickness between signal layers for impedance matching within a layer of substrate. More significantly, the applied layer of low loss capacitive materials can simultaneously act as a capacitor as well as a dielectric for separation of signal layers.

    摘要翻译： 由热固性树脂，热塑性树脂，交联剂组成的含有钛酸钡的铁电陶瓷纳米粒子的低损耗电容和低损耗绝缘介电材料。 组合的低损耗绝缘电介质层和由该材料产生的低损耗电容层允许一个连续的层可以形成内部电容器并且允许改变信号层之间的介电厚度以在衬底层内进行阻抗匹配。 更重要的是，所应用的低损耗电容材料层可以同时充当电容器以及用于分离信号层的电介质。

    Solid via layer to layer interconnect
    2.
    发明授权
    Solid via layer to layer interconnect 失效
    实体通过层间互连

    公开(公告)号：US07076869B2

    公开(公告)日：2006-07-18

    申请号：US10260153

    申请日：2002-09-27

    申请人： Brian E. Curcio ,  Donald S. Farquhar ,  Voya R. Markovich ,  Konstantinos I. Papathomas

    发明人： Brian E. Curcio ,  Donald S. Farquhar ,  Voya R. Markovich ,  Konstantinos I. Papathomas

    IPC分类号： H01K3/10

    CPC分类号： H05K3/462 ,  H05K3/321 ,  H05K3/423 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

    摘要： The present invention relates to a method for providing an interconnect between layers of a multilayer circuit board. A first via extending through a total thickness of a first layer is formed. The first via is totally filled with a first solid conductive plug and an end of the first solid conductive plug includes a first contact pad that is in contact with a surface of the first layer. A second via extending through a total thickness of a second layer is formed. The second via totally filling with a second solid conductive plug and an end of the second solid conductive plug includes a second contact pad that is in contact with a surface of the second layer. The second layer is electrically and mechanically coupled to the first layer by an electrically conductive adhesive that is in electrical and mechanical contact with both the end of the first plug and the end of the second plug.

    摘要翻译： 本发明涉及一种在多层电路板的层之间提供互连的方法。 形成延伸通过第一层的总厚度的第一通孔。 第一通孔完全填充有第一固体导电插塞，并且第一固体导电插塞的端部包括与第一层的表面接触的第一接触垫。 形成延伸穿过第二层的总厚度的第二通孔。 通过完全填充第二固体导电插塞和第二固体导电插塞的端部的第二通孔包括与第二层的表面接触的第二接触垫。 第二层通过与第一插头的端部和第二插头的端部电接触和机械接触的导电粘合剂电和机械地耦合到第一层。

    Resin composition with a polymerizing agent and method of manufacturing prepreg and other laminate structures therefrom
    4.
    发明授权
    Resin composition with a polymerizing agent and method of manufacturing prepreg and other laminate structures therefrom 有权
    具有聚合剂的树脂组合物及其制备预浸料及其它层合结构的方法

    公开(公告)号：US06734259B1

    公开(公告)日：2004-05-11

    申请号：US10281038

    申请日：2002-10-24

    申请人： Robert M. Japp ,  Konstantinos I. Papathomas ,  Cory J. Ruud

    发明人： Robert M. Japp ,  Konstantinos I. Papathomas ,  Cory J. Ruud

    IPC分类号： C08F28308

    CPC分类号： C08G65/485 ,  C08F283/08 ,  C08L71/126 ,  C08L2666/20

    摘要： A prepreg resin comprising: (a) 98 to 40% by weight based on the total weight of components (a) and (b), of a curable polyphenylene ether resin; (b) 2 to 60% by weight based on the total weight of components (a) and (b), of at least one cyanurate selected from the group consisting of triallyl isocyanurate and triallyl cyanurate; (c) a polymerization initiator comprised of a peroxide functionalized polymer, said peroxide functionalized polymer being fragmented by heat to a plurality of free radical moieties, such as t-butoxide moieties, and a relatively inert moiety having a molecular weight greater than about 1,000. The invention also encompasses a cured resin either as a coating on a substrate, without fiberglass cloth embedded, or a cured prepreg with fiberglass cloth embedded and a method of forming the same.

    摘要翻译： 一种预浸料树脂，其包含：（a）基于组分（a）和（b）的总重量的98-40重量％的可固化聚苯醚树脂;（b）基于总重量的2-60重量％ 的组分（a）和（b））中的至少一种选自三烯丙基异氰脲酸酯和氰尿酸三烯丙酯的氰脲酸酯;（c）由过氧化物官能化聚合物组成的聚合引发剂，所述过氧化物官能化聚合物被加热分解成 多个自由基部分，例如叔丁醇部分，以及分子量大于约1,000的相对惰性的部分。本发明还包括固化树脂，作为基材上的涂层，无玻璃纤维布嵌入或固化 嵌入玻璃纤维布的预浸料及其形成方法。

    Plate for liquid crystal display, method and polymeric compositions
    7.
    发明授权
    Plate for liquid crystal display, method and polymeric compositions 有权
    液晶显示板，方法和聚合物组合物

    公开(公告)号：US06444407B1

    公开(公告)日：2002-09-03

    申请号：US09603197

    申请日：2000-06-26

    申请人： Richard A. Day ,  Ramesh R. Kodnani ,  Konstantinos I. Papathomas

    发明人： Richard A. Day ,  Ramesh R. Kodnani ,  Konstantinos I. Papathomas

    IPC分类号： G02F11335

    CPC分类号： G02F1/133512 ,  G02F1/13336

    摘要： Plates that are especially suitable for use in liquid crystal display structures comprising a transparent substrate; a dark mesh material on the substrate having a thickness of about 1 to about 30 microns; wherein the dark mesh material comprises a photocured photoimageable organic polymeric composition and a coloring agent; and wherein the dark mesh material has an optical density of about 0.5 to about 3 in the visible light range; and a polarizing layer are provided along with methods for their fabrication.

    摘要翻译： 特别适用于包括透明基板的液晶显示结构的板; 基底上的黑色网状材料，其厚度为约1至约30微米; 其中所述黑色网状材料包含光固化可光成像的有机聚合物组合物和着色剂; 并且其中所述黑色网状材料在可见光范围内具有约0.5至约3的光密度; 并提供偏振层及其制造方法。

    Multilayer capacitance structure and circuit board containing the same
    9.
    发明授权
    Multilayer capacitance structure and circuit board containing the same 失效
    包含多层电容结构和电路板

    公开(公告)号：US06343001B1

    公开(公告)日：2002-01-29

    申请号：US09655381

    申请日：2000-09-05

    申请人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

    发明人： Robert M. Japp ,  John M. Lauffer ,  Konstantinos I. Papathomas

    IPC分类号： H01G4228

    CPC分类号： H05K1/162 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0759

    摘要： A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

    摘要翻译： 提供了一种从芯结构形成电容性芯结构和形成电路化印刷线路板的方法及其结构。 通过提供导电材料片的中心导电平面并在中心导电平面中形成至少一个间隙孔来形成电容芯结构。 第一和第二外部导电平面在第一和第二外部平面之间的介电材料膜和中心导电平面之间层压到接地平面的相对侧。 在第一和第二外部平面的每一个中形成至少一个间隙孔。 可以通过在两个电路化结构之间层叠电容性芯结构来形成电路化布线板结构。 本发明还涉及通过这些方法形成的结构。