公开(公告)号：US5189261A

公开(公告)日：1993-02-23

申请号：US598466

申请日：1990-10-09

申请人： Lawrence C. Alexander ,  Bernd K. Appelt ,  David K. Balkin ,  James J. Hansen ,  Joseph Hromek ,  Ronald A. Kaschak ,  John M. Lauffer ,  Irving Memis ,  Magan S. Patel ,  Andrew M. Seman ,  Robin A. Susko

发明人： Lawrence C. Alexander ,  Bernd K. Appelt ,  David K. Balkin ,  James J. Hansen ,  Joseph Hromek ,  Ronald A. Kaschak ,  John M. Lauffer ,  Irving Memis ,  Magan S. Patel ,  Andrew M. Seman ,  Robin A. Susko

IPC分类号： H05K1/11 ,  H01L23/538 ,  H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K3/44 ,  H05K7/20

CPC分类号： H01L23/5384 ,  H05K3/4038 ,  H05K3/4046 ,  H05K3/44 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K2201/09554 ,  H05K2201/10234 ,  H05K2201/10303 ,  H05K2201/10401 ,  H05K2201/10871 ,  H05K2203/107 ,  H05K2203/1105 ,  H05K2203/128 ,  H05K3/0035 ,  Y10S428/901 ,  Y10T29/49155

摘要： Circuit boards or cards containing metallic layers on opposite major surfaces of a dielectric substrate whereby electrical and/or thermal interconnection between the metallic layers is provided in vias that extend through one of the metallic layers, and the dielectric substrate and into the other metallic layer.

摘要翻译： 电介质基板的相对的主表面上包含金属层的电路板或卡片，从而在金属层之间提供电和/或热互连，其通孔延伸穿过金属层之一以及电介质基板并进入另一金属层。

公开(公告)号：US06429390B1

公开(公告)日：2002-08-06

申请号：US09804535

申请日：2001-03-12

申请人： Michael J. Cummings ,  Robert J. Lerner ,  Michael V. Longo ,  Andrew M. Seman ,  Raymond C. Tompkins ,  Timothy L. Wells

发明人： Michael J. Cummings ,  Robert J. Lerner ,  Michael V. Longo ,  Andrew M. Seman ,  Raymond C. Tompkins ,  Timothy L. Wells

IPC分类号： H01R1204

CPC分类号： H05K1/114 ,  H05K1/0269 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/09745 ,  H05K2201/10734

摘要： A wiring board for mounting an electrical device, which has an array of connectors thereon arranged in a grid pattern, wherein the connectors have at least two levels of criticality of connection to the substrate. The substrate has a plurality of mounting structure or features arranged in the same grid pattern to connect with the array of connectors on the electrical device. The mounting structures or features are divided into a plurality of at least two groups, with each group corresponding to a level of criticality of the connectors on the device. Each group of mounting structures has a discernible feature differing from each other group, to thereby permit different levels of inspection criteria for each group. The invention also contemplates a method of forming a substrate having the features for connecting the connectors on the device that have different levels of criticality

摘要翻译： 一种用于安装电气装置的布线板，其具有以栅格图案布置的连接器阵列，其中所述连接器具有至少两个级别的与所述基板的连接关键性。 衬底具有以相同格栅图案布置的多个安装结构或特征，以与电气设备上的连接器阵列连接。 安装结构或特征被分成多个至少两个组，每个组对应于装置上连接器的关键性水平。 每组安装结构具有彼此不同的可辨别特征，从而允许每组的不同级别的检查标准。 本发明还考虑了一种形成具有用于连接具有不同等级临界度的装置上的连接器的特征的基板的方法

公开(公告)号：US06931722B2

公开(公告)日：2005-08-23

申请号：US10395944

申请日：2003-03-24

申请人： Edward L. Arrington ,  Anilkumar C. Bhatt ,  Edmond O. Fey ,  Kevin T. Knadle ,  John J. Konrad ,  Joseph A Kotylo ,  Jeffrey McKeveny ,  Jose A. Rios ,  Amit K. Sarkhel ,  Andrew M. Seman ,  Timothy L. Wells

发明人： Edward L. Arrington ,  Anilkumar C. Bhatt ,  Edmond O. Fey ,  Kevin T. Knadle ,  John J. Konrad ,  Joseph A Kotylo ,  Jeffrey McKeveny ,  Jose A. Rios ,  Amit K. Sarkhel ,  Andrew M. Seman ,  Timothy L. Wells

IPC分类号： H05K3/24 ,  H05K3/28 ,  H05K3/34 ,  H05K3/42 ,  H05K3/02

CPC分类号： H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/42 ,  H05K2201/0391 ,  H05K2203/0315 ,  H05K2203/0574 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

摘要翻译： 公开了一种制造印刷电路器件的方法，该印刷电路器件包括电绝缘衬底以及形成在衬底顶表面上的第一组，第二组和第三组导体。 该方法包括在第二导体组上形成氧化物层; 在氧化物层上形成焊料掩模; 在第一组导体上形成复合层; 以及在所述第三组导体的至少一部分上形成焊料层。

公开(公告)号：US06586683B2

公开(公告)日：2003-07-01

申请号：US09844814

申请日：2001-04-27

申请人： Edward L. Arrington ,  Anilkumar C. Bhatt ,  Edmond O. Fey ,  Kevin T. Knadle ,  John J. Konrad ,  Joseph A. Kotylo ,  Jeffrey McKeveny ,  Jose A. Rios ,  Amit K. Sarkhel ,  Andrew M. Seman ,  Timothy L. Wells

发明人： Edward L. Arrington ,  Anilkumar C. Bhatt ,  Edmond O. Fey ,  Kevin T. Knadle ,  John J. Konrad ,  Joseph A. Kotylo ,  Jeffrey McKeveny ,  Jose A. Rios ,  Amit K. Sarkhel ,  Andrew M. Seman ,  Timothy L. Wells

IPC分类号： H05K103

CPC分类号： H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/42 ,  H05K2201/0391 ,  H05K2203/0315 ,  H05K2203/0574 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

公开(公告)号：US07596862B2

公开(公告)日：2009-10-06

申请号：US11863820

申请日：2007-09-28

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

公开(公告)号：US07325299B2

公开(公告)日：2008-02-05

申请号：US11619789

申请日：2007-01-04

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.

摘要翻译： 制造电路化基板的方法。 具有基本平坦的上表面的导电层形成在基板的上表面上并与基板的上表面直接机械接触。 去除导电层的一部分以在导电层中形成临时侧壁。 在基本平坦的上表面和临时侧壁上形成可图案化材料层。 去除导电层上图案化材料层的一部分以露出临时侧壁。 去除基本平坦的上表面的一部分以在可图案材料层中形成侧壁。 去除导电层中的临时侧壁的部分以形成由衬底的上表面限定的第二侧壁和底壁。 第二侧壁基本上垂直于底壁。

公开(公告)号：US07185428B2

公开(公告)日：2007-03-06

申请号：US10738705

申请日：2003-12-16

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H05K3/02

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。

公开(公告)号：US06822332B2

公开(公告)日：2004-11-23

申请号：US10253439

申请日：2002-09-23

申请人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

发明人： Frank D. Egitto ,  Kevin T. Knadle ,  Andrew M. Seman

IPC分类号： H01L2348

CPC分类号： H05K3/06 ,  B32B15/08 ,  B32B15/20 ,  B32B27/04 ,  B32B27/06 ,  B32B27/30 ,  B32B27/38 ,  H01L21/32134 ,  H01L21/4846 ,  H01L21/76838 ,  H01L2924/0002 ,  H05K3/027 ,  H05K3/061 ,  H05K3/064 ,  H05K2203/0369 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322 ,  Y10T428/24802 ,  H01L2924/00

摘要： A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

摘要翻译： 提供电路化基板和制造电路化基板的方法。 电路化基板包括具有基本平坦的上表面的基板和位于基本平坦的上表面上的导电层。 导电层包括其中的至少一个侧壁，在导电层中限定开口。 所述导电层包括与所述开口间隔开的端部，所述端部与所述基板的大致平坦的上表面形成锐角。 所述至少一个侧壁基本上垂直于所述基底的基本平坦的上表面。