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    Chip carrier with reduced interference signal sensitivity
    7.
    发明授权
    Chip carrier with reduced interference signal sensitivity 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号：US07911026B2

    公开(公告)日：2011-03-22

    申请号：US11618172

    申请日：2006-12-29

    申请人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    发明人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    IPC分类号： H01L21/02

    CPC分类号： H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/4602 ,  H01L2224/05599

    摘要： Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译： 载体包括：具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道，其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上的前侧布线层， 具有形成在其中的第一前侧金属化层，使得其包括用于将微电子器件和/或电路电连接到信号或电源电压的第一极的第一电容器电极。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域，该区域至少部分地形成第二电容器电极，用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。

    Method of making an integrated circuit including singulating a semiconductor wafer
    8.
    发明授权
    Method of making an integrated circuit including singulating a semiconductor wafer 有权
    制造包括单片化半导体晶片的集成电路的方法

    公开(公告)号：US07674689B2

    公开(公告)日：2010-03-09

    申请号：US11858437

    申请日：2007-09-20

    申请人： Manfred Schneegans ,  Werner Kroninger

    发明人： Manfred Schneegans ,  Werner Kroninger

    IPC分类号： H01L21/46

    CPC分类号： H01L21/78

    摘要： A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.

    摘要翻译： 制造集成电路的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体晶片，第一表面和第二表面中的至少一个包括沉积在表面上的金属化层。 该方法还包括在半导体晶片中形成从第一表面和第二表面中的一个向第一表面和第二表面中的另一个延伸的第一沟槽。 该方法还包括锯切另一表面中的第二沟槽，直到第二沟槽与第一沟槽连通，从而从半导体晶片分离集成电路。