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    Chip carrier with reduced interference signal sensitivity
    5.
    发明授权
    Chip carrier with reduced interference signal sensitivity 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号：US07911026B2

    公开(公告)日：2011-03-22

    申请号：US11618172

    申请日：2006-12-29

    申请人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    发明人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    IPC分类号： H01L21/02

    CPC分类号： H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/4602 ,  H01L2224/05599

    摘要： Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译： 载体包括：具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道，其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上的前侧布线层， 具有形成在其中的第一前侧金属化层，使得其包括用于将微电子器件和/或电路电连接到信号或电源电压的第一极的第一电容器电极。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域，该区域至少部分地形成第二电容器电极，用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。

    Method of making an integrated circuit including singulating a semiconductor wafer
    6.
    发明授权
    Method of making an integrated circuit including singulating a semiconductor wafer 有权
    制造包括单片化半导体晶片的集成电路的方法

    公开(公告)号：US07674689B2

    公开(公告)日：2010-03-09

    申请号：US11858437

    申请日：2007-09-20

    申请人： Manfred Schneegans ,  Werner Kroninger

    发明人： Manfred Schneegans ,  Werner Kroninger

    IPC分类号： H01L21/46

    CPC分类号： H01L21/78

    摘要： A method of making an integrated circuit includes providing a semiconductor wafer having a first surface and a second surface opposite the first surface, at least one of the first surface and the second surface including a metallization layer deposited onto the surface. The method additionally includes forming a first trench in the semiconductor wafer extending from one of the first surface and the second surface toward an other of the first surface and the second surface. The method further includes sawing a second trench in the other surface until the second trench communicates with the first trench, thus singulating the integrated circuit from the semiconductor wafer.

    摘要翻译： 制造集成电路的方法包括提供具有第一表面和与第一表面相对的第二表面的半导体晶片，第一表面和第二表面中的至少一个包括沉积在表面上的金属化层。 该方法还包括在半导体晶片中形成从第一表面和第二表面中的一个向第一表面和第二表面中的另一个延伸的第一沟槽。 该方法还包括锯切另一表面中的第二沟槽，直到第二沟槽与第一沟槽连通，从而从半导体晶片分离集成电路。

    Production method for a semiconductor component
    8.
    发明授权
    Production method for a semiconductor component 有权
    半导体部件的制造方法

    公开(公告)号：US06919269B2

    公开(公告)日：2005-07-19

    申请号：US10477620

    申请日：2002-04-11

    申请人： Manfred Schneegans ,  Wolfgang Jäger ,  Ulrike Bewersdorff-Sarlette ,  Stephan Wege

    发明人： Manfred Schneegans ,  Wolfgang Jäger ,  Ulrike Bewersdorff-Sarlette ,  Stephan Wege

    IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  H01L21/44

    CPC分类号： H01L29/4933 ,  H01L21/28061 ,  H01L21/321

    摘要： A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

    摘要翻译： 一种用于制造半导体部件的方法包括：在衬底上沉积多晶硅层，在多晶硅层上沉积前体层，以及在前体层上沉积保护层。 在第一温度下在前体层中发生结晶转变以形成电极层。 图案化层以形成电极堆叠，并且多晶硅层在第二温度下被氧化，使得在电极层中不发生结晶转变。

    Methods for fabricating a contact for an integrated circuit
    9.
    发明授权
    Methods for fabricating a contact for an integrated circuit 失效
    制造集成电路接点的方法

    公开(公告)号：US06903009B2

    公开(公告)日：2005-06-07

    申请号：US10364070

    申请日：2003-02-11

    申请人： Alexander Ruf ,  Manfred Schneegans

    发明人： Alexander Ruf ,  Manfred Schneegans

    IPC分类号： G11C5/06 ,  H01L21/283 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L31/0336

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to one embodiment, a method for fabricating a contact is provided. The method can include a step of depositing a Ti layer in order to completely fill a contact hole and on a surrounding surface of an insulation layer. The method can also include a step of partially converting the Ti layer into a TiN layer in such a manner that a TiN layer is provided on the top side in the contact hole. Further, the method can include a step of polishing back the Ti layer and any remaining TiN layer on the surrounding surface of the insulation layer in a single-stage polishing step.

    摘要翻译： 根据一个实施例，提供了一种用于制造触点的方法。 该方法可以包括沉积Ti层以完全填充接触孔和绝缘层的周围表面的步骤。 该方法还可以包括将Ti层部分地转化为TiN层的步骤，即在接触孔的顶侧设置有TiN层。 此外，该方法可以包括在单级抛光步骤中抛光Ti层和在绝缘层的周围表面上的任何剩余的TiN层的步骤。