公开(公告)号：US06348741B1

公开(公告)日：2002-02-19

申请号：US09675011

申请日：2000-09-29

申请人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

发明人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

IPC分类号： H01L2348

CPC分类号： H01L23/3171 ,  H01L23/293 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.

摘要翻译： 制造方法使得可以以高的制造成品率制造突出的安装可靠性的半导体装置。 一种半导体装置，其中在其上形成有电路和电极的半导体芯片的表面上设置有应力缓冲层，除了电极的部分具有连接到电极上的布线层的应力 缓冲层，布线层上的外部保护膜和应力缓冲层，布线层的一部分在外部保护膜的预定位置露出的窗口，以及外部电极，其与布线层电连接，经由 窗户。 应力缓冲层，布线层，导体，外部保护膜和外部电极形成在半导体芯片的端部的内侧。

公开(公告)号：US06621154B1

公开(公告)日：2003-09-16

申请号：US09671364

申请日：2000-09-28

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Takao Miwa ,  Akira Nagai ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Takao Miwa ,  Akira Nagai ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L2329

CPC分类号： H01L23/293 ,  C08L9/02 ,  C08L13/00 ,  C08L63/00 ,  H01L23/485 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/13022 ,  H01L2924/0002 ,  H01L2924/09701 ,  C08L2666/08 ,  H01L2224/05552

摘要： A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.

摘要翻译： 一种微型半导体装置在耐回流性，温度循环特性以及PCT电阻方面具有突出优点，其对应于高密度填料，高密度化和加工加速。 所述半导体装置具有在半导体元件上具有至少一个应力缓冲层，所述至少一个应力缓冲层具有形成有电极焊盘的电极焊盘，所述电极焊盘在所述应力缓冲层上具有导体，所述导体用于通过穿过所述应力缓冲层的通孔 所述电极焊盘和所述导体在导体上具有外部电极，并且在外部电极存在的区域以外的区域和在导体上具有导体保护层的应力缓冲层，其中应力缓冲层包括交联丙烯腈 丁二烯橡胶，其具有在25℃下为固体的环氧树脂和羧基。

公开(公告)号：US06888230B1

公开(公告)日：2005-05-03

申请号：US09429297

申请日：1999-10-28

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/12 ,  H01L21/301 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块，其中：半导体器件具有小的翘曲; 几乎不产生芯片边缘的损伤和在滴下试验中发生的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 该半导体包括半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US06627997B1

公开(公告)日：2003-09-30

申请号：US09463431

申请日：2000-01-27

申请人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

发明人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

IPC分类号： H01L2348

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the semiconductor chips are covered with a single heat spread plate, and the whole space around the semiconductor chips, sandwiched between the wiring board and the heat spread plate, is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

摘要翻译： 在多芯片模块中，多个半导体芯片安装在单个布线板上。 半导体芯片的上表面被单个扩散板覆盖，并且夹在布线板和扩散板之间的半导体芯片周围的整个空间填充有树脂。 半导体芯片通过树脂相互连接，从而分散施加在任何芯片上的任何应力。 这减少了由应力集中引起的裂纹的发生。 由于半导体芯片和热扩散板与树脂粘合在一起，即使芯片的尺寸有变化，两者也可以容易地结合。 此外，所有芯片和散热板的接合可以在单个工艺中完成。

公开(公告)号：US06940162B2

公开(公告)日：2005-09-06

申请号：US10840605

申请日：2004-05-07

申请人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

发明人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

IPC分类号： H01L21/56 ,  H01L23/42 ,  H01L23/433 ,  H01L25/065 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/42 ,  H01L21/56 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/20752

摘要： In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin.By so doing, the semiconductor chips are interconnected through the resin, so that even if a stress is exerted on any of the chips, it is dispersed and therefore it is possible to diminish the occurrence of cracks in the chips and the heat spread plate caused by stress concentration. Besides, since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

摘要翻译： 在多个裸片或封装的半导体芯片安装在单个布线板上并且半导体芯片的上表面被一个单独的散热板覆盖的结构的多芯片模块中，由此夹在半导体芯片周围的整个空间 布线板和扩散板填充树脂。 通过这样做，半导体芯片通过树脂互连，使得即使在任何芯片上施加应力，它也被分散，因此可以减少芯片和散热板中的裂纹的发生 通过压力集中。 此外，由于半导体芯片和扩散板与树脂粘合在一起，即使芯片的尺寸有变化，两者也可以容易地结合。 此外，所有芯片和散热板的接合可以在单个工艺中完成。

公开(公告)号：US06784541B2

公开(公告)日：2004-08-31

申请号：US10302986

申请日：2002-11-25

申请人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

发明人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

IPC分类号： H01L2334

CPC分类号： H01L23/42 ,  H01L21/56 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/20752

摘要： In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

摘要翻译： 在多芯片模块中，多个半导体芯片安装在单个布线板上。 芯片的上表面被单个散热板覆盖，并且夹在布线板和扩散板之间的芯片周围的整个空间填充有树脂。 半导体芯片通过树脂相互连接，从而分散施加在任何芯片上的任何应力。 这减少了由应力集中引起的裂纹的发生。 由于芯片和扩散板与树脂粘合在一起，即使芯片的尺寸有变化，两者也可以容易地结合。 此外，所有芯片和散热板的接合可以在单个工艺中完成。

公开(公告)号：US07217992B2

公开(公告)日：2007-05-15

申请号：US10861523

申请日：2004-06-07

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/02 ,  H01L23/28 ,  H01L21/00

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块：其中半导体器件具有小的翘曲; 几乎不产生芯片边缘的损坏和跌落试验中的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 半导体器件17包括：半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US20050245061A1

公开(公告)日：2005-11-03

申请号：US11168460

申请日：2005-06-29

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L23/29 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L21/50

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

摘要翻译： 本发明是一种具有半导体元件的半导体器件，该半导体器件通过沿着划线在一侧形成电极焊盘切割半导体晶片而获得，半导体元件保护层在半导体元件上具有在该焊盘上的开口，应力缓冲 在该焊盘上具有开口的层上的引线部分，经由开口从电极焊盘到达层的引线部分，引线部分上的外部电极和层上的导体保护层，层和导体保护层 层，形成在划线内的半导体元件的端面上的各个端面，并露出从端面的端面到划线的内侧的范围。

公开(公告)号：US07378333B2

公开(公告)日：2008-05-27

申请号：US11168460

申请日：2005-06-29

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L21/301

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

摘要翻译： 本发明是一种具有半导体元件的半导体器件，该半导体器件通过沿着划线在一侧形成电极焊盘切割半导体晶片而获得，半导体元件保护层在半导体元件上具有在该焊盘上的开口，应力缓冲 在该焊盘上具有开口的层上的引线部分，经由开口从电极焊盘到达层的引线部分，引线部分上的外部电极和层上的导体保护层，层和导体保护层 层，形成在划线内的半导体元件的端面上的各个端面，并露出从端面的端面到划线的内侧的范围。

公开(公告)号：US06946723B2

公开(公告)日：2005-09-20

申请号：US09809181

申请日：2001-03-16

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L23/29 ,  H01L21/301 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/495

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.

摘要翻译： 具有半导体元件的半导体器件通过沿着划线切割具有在其一侧形成的电极焊盘的半导体晶片来获得。 半导体器件在半导体元件上具有半导体元件保护层，以便在焊盘上形成开口，该层上的应力缓冲层在焊盘上形成开口，从电极到达该层的引线部分 通过开口焊盘，引线部分上的外部电极以及该层上的导体保护层。 层，层和导体保护层在划线内部的半导体元件的端面上形成相应的端面，并将半导体元件的表面从端表面的端面暴露于刻痕内侧 线，从而暴露划线。