公开(公告)号：US06888230B1

公开(公告)日：2005-05-03

申请号：US09429297

申请日：1999-10-28

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/12 ,  H01L21/301 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/28 ,  H01L23/31 ,  H01L23/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块，其中：半导体器件具有小的翘曲; 几乎不产生芯片边缘的损伤和在滴下试验中发生的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 该半导体包括半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US07217992B2

公开(公告)日：2007-05-15

申请号：US10861523

申请日：2004-06-07

申请人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Masahiko Ogino ,  Takumi Ueno ,  Shuji Eguchi ,  Akira Nagai ,  Toshiya Satoh ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Tadanori Segawa ,  Nobutake Tsuyuno ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L23/02 ,  H01L23/28 ,  H01L21/00

CPC分类号： H01L23/3171 ,  H01L23/3114 ,  H01L23/3164 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2924/00012

摘要： Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.

摘要翻译： 提供半导体器件，半导体晶片和半导体模块：其中半导体器件具有小的翘曲; 几乎不产生芯片边缘的损坏和跌落试验中的裂纹; 半导体装置的安装可靠性和大规模生产性优异。 半导体器件17包括：半导体芯片64; 设置在半导体芯片的形成有电路和电极的平面上的多孔应力缓和层3; 设置在应力缓和层上并与电极连接的电路层2; 和设置在电路层上的外部端子10; 其中在半导体芯片的与应力缓和层相反的平面上形成有机保护膜7，并且应力缓和层，半导体芯片6和保护膜7的各个侧面在外部暴露在外部 飞机

公开(公告)号：US06433440B1

公开(公告)日：2002-08-13

申请号：US09092138

申请日：1998-06-05

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了降低半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高批量生产 容量和提高包装可靠性。

公开(公告)号：US07038325B2

公开(公告)日：2006-05-02

申请号：US10830051

申请日：2004-04-23

申请人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

发明人： Masahiko Ogino ,  Shuji Eguchi ,  Akira Nagai ,  Takumi Ueno ,  Masanori Segawa ,  Hiroyoshi Kokaku ,  Toshiaki Ishii ,  Ichiro Anjoh ,  Asao Nishimura ,  Chuichi Miyazaki ,  Mamoru Mita ,  Norio Okabe

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3107 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L2224/29111 ,  H01L2224/73215 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2224/29099 ,  H01L2924/00

摘要： In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

摘要翻译： 在具有三层缓冲层的半导体器件中，作为在半导体芯片5和布线4之间的应力缓冲层，芯层1具有三维网状结构的互连泡沫的芯层1和设置在芯层两侧的粘合层2 为了减小半导体器件与封装衬底之间产生的热应力，其中芯层1与总缓冲层的厚度比至少为0.2，可以通过使用这种缓冲层来简化制造工艺，从而提高质量 生产能力和提高包装可靠性。

公开(公告)号：US6097100A

公开(公告)日：2000-08-01

申请号：US915334

申请日：1997-08-20

申请人： Shuji Eguchi ,  Yasuhide Sugawara ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Akira Nagai ,  Ryou Moteki ,  Ogino Masahiko ,  Masanori Segawa ,  Rie Hattori ,  Nobutake Tsuyuno ,  Takumi Ueno ,  Atsushi Nakamura ,  Asao Nishimura

发明人： Shuji Eguchi ,  Yasuhide Sugawara ,  Toshiaki Ishii ,  Hiroyoshi Kokaku ,  Akira Nagai ,  Ryou Moteki ,  Ogino Masahiko ,  Masanori Segawa ,  Rie Hattori ,  Nobutake Tsuyuno ,  Takumi Ueno ,  Atsushi Nakamura ,  Asao Nishimura

IPC分类号： H01L23/29 ,  H01L23/31 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L23/4951 ,  H01L23/293 ,  H01L23/3128 ,  H01L2224/05624 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/181

摘要： A resin encapsulated semiconductor element is encapsulated with resin composition containing an organic compound selected from the group consisting of organobromine compounds, organophosphorus compounds and organonitrogen compounds, an inorganic filler, and a metal borate. The obtained resin encapsulated semiconductor element has the same flame resistance as a conventional semiconductor element which is encapsulated with a resin composition containing a halogen and antimony compound, and furthermore, has remarkably improved reliabilities regarding moisture resistance and storing at a high temperature by effects of the contained metal borate for suppressing generation of or trapping released gas components, such as halogen or phosphorus, and others.

摘要翻译： 树脂封装的半导体元件用含有有机化合物的树脂组合物包封，所述有机化合物选自有机溴化合物，有机磷化合物和有机氮化合物，无机填料和金属硼酸盐。 所获得的树脂封装的半导体元件具有与用含有卤素和锑化合物的树脂组合物封装的常规半导体元件相同的阻燃性，并且还具有显着提高的耐湿性的可靠性和高温下的存储 含有金属硼酸盐，用于抑制诸如卤素或磷的释放气体组分的产生或捕获等。

公开(公告)号：US06348741B1

公开(公告)日：2002-02-19

申请号：US09675011

申请日：2000-09-29

申请人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

发明人： Masahiko Ogino ,  Takao Miwa ,  Toshiya Satoh ,  Akira Nagai ,  Tadanori Segawa ,  Akihiro Yaguchi ,  Ichiro Anjo ,  Asao Nishimura ,  Takumi Ueno

IPC分类号： H01L2348

CPC分类号： H01L23/3171 ,  H01L23/293 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.

摘要翻译： 制造方法使得可以以高的制造成品率制造突出的安装可靠性的半导体装置。 一种半导体装置，其中在其上形成有电路和电极的半导体芯片的表面上设置有应力缓冲层，除了电极的部分具有连接到电极上的布线层的应力 缓冲层，布线层上的外部保护膜和应力缓冲层，布线层的一部分在外部保护膜的预定位置露出的窗口，以及外部电极，其与布线层电连接，经由 窗户。 应力缓冲层，布线层，导体，外部保护膜和外部电极形成在半导体芯片的端部的内侧。

公开(公告)号：US06396145B1

公开(公告)日：2002-05-28

申请号：US09446979

申请日：1999-12-30

申请人： Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L2348

CPC分类号： H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the in semiconductor element, bump electrodes for external connection electrically connected to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions.

摘要翻译： 半导体器件包括布置成形成集成电路的半导体元件，形成在半导体元件的集成电路形成表面侧的多个电极焊盘，用于通过导电层电连接到电极焊盘的用于外部连接的凸起电极， 以及一方面在集成电路形成表面和电极焊盘之间形成的应力松弛层，另一方面在凸起电极和导电层之间形成应力松弛层，应力松弛层粘附到其上，其中来自一个或多个应力松弛层的三分之一以上 其表面被切除以除去，并且其中应力松弛层被细分为多个区域。

公开(公告)号：US06710446B2

公开(公告)日：2004-03-23

申请号：US10136305

申请日：2002-05-02

申请人： Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

发明人： Akira Nagai ,  Takumi Ueno ,  Haruo Akahoshi ,  Syuji Eguchi ,  Masahiko Ogino ,  Toshiya Satoh ,  Asao Nishimura ,  Ichiro Anjoh

IPC分类号： H01L2348

CPC分类号： H01L23/3114 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02145 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/08225 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof, which device includes a semiconductor element arranged to form integrated circuitry, a plurality of electrode pads formed on the side of the integrated circuitry formation surface of the semiconductor element, bump electrodes for electrically connecting to the electrode pads through a conductive layer, and a stress relaxation layer formed between the integrated circuitry formation surface and electrode pads on one hand and the bump electrodes and conductive layer on the other hand, the stress relaxation layer being adhered thereto, wherein more than one third of the stress relaxation layer from a surface thereof is cut away for removal and wherein the stress relaxation layer is subdivided into a plurality of regions. Accordingly, it is possible to provide a semiconductor device capable of offering high density mounting schemes with increased reliability while reducing production costs.

摘要翻译： 一种半导体器件及其制造方法，该器件包括布置成形成集成电路的半导体元件，形成在半导体元件的集成电路形成表面侧的多个电极焊盘，用于电连接到电极焊盘的凸起电极 通过导电层和在集成电路形成表面和电极焊盘之间形成的应力松弛层，另一方面，凸块电极和导电层，应力松弛层粘附到其上，其中超过三分之一 将其表面的应力松弛层切除以除去，其中应力松弛层被细分成多个区域。 因此，可以提供能够提供可靠性高的高密度安装方案的半导体器件，同时降低生产成本。

公开(公告)号：US06784541B2

公开(公告)日：2004-08-31

申请号：US10302986

申请日：2002-11-25

申请人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

发明人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

IPC分类号： H01L2334

CPC分类号： H01L23/42 ,  H01L21/56 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/20752

摘要： In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the chips are covered with a single heat spread plate, and the whole space around the chips sandwiched between the wiring board and the heat spread plate is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

摘要翻译： 在多芯片模块中，多个半导体芯片安装在单个布线板上。 芯片的上表面被单个散热板覆盖，并且夹在布线板和扩散板之间的芯片周围的整个空间填充有树脂。 半导体芯片通过树脂相互连接，从而分散施加在任何芯片上的任何应力。 这减少了由应力集中引起的裂纹的发生。 由于芯片和扩散板与树脂粘合在一起，即使芯片的尺寸有变化，两者也可以容易地结合。 此外，所有芯片和散热板的接合可以在单个工艺中完成。

公开(公告)号：US06627997B1

公开(公告)日：2003-09-30

申请号：US09463431

申请日：2000-01-27

申请人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

发明人： Shuji Eguchi ,  Akira Nagai ,  Haruo Akahoshi ,  Takumi Ueno ,  Toshiya Satoh ,  Masahiko Ogino ,  Asao Nishimura ,  Ichiro Anjo ,  Hideki Tanaka

IPC分类号： H01L2348

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

摘要： In a multi-chip module, a plurality of semiconductor chips are mounted on a single wiring board. Upper surfaces of the semiconductor chips are covered with a single heat spread plate, and the whole space around the semiconductor chips, sandwiched between the wiring board and the heat spread plate, is filled with resin. The semiconductor chips are interconnected through the resin so that any stress exerted on any chips is dispersed. This diminishes the occurrence of cracks caused by stress concentration. Since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.

摘要翻译： 在多芯片模块中，多个半导体芯片安装在单个布线板上。 半导体芯片的上表面被单个扩散板覆盖，并且夹在布线板和扩散板之间的半导体芯片周围的整个空间填充有树脂。 半导体芯片通过树脂相互连接，从而分散施加在任何芯片上的任何应力。 这减少了由应力集中引起的裂纹的发生。 由于半导体芯片和热扩散板与树脂粘合在一起，即使芯片的尺寸有变化，两者也可以容易地结合。 此外，所有芯片和散热板的接合可以在单个工艺中完成。