公开(公告)号：US20090134498A1

公开(公告)日：2009-05-28

申请号：US12273590

申请日：2008-11-19

申请人： Hiroaki IKEDA ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama ,  Yasuhiro Naka ,  Nae Hisano ,  Hisashi Tanie ,  Kunihiko Nishi ,  Hiroyuki Tenmei

发明人： Hiroaki IKEDA ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama ,  Yasuhiro Naka ,  Nae Hisano ,  Hisashi Tanie ,  Kunihiko Nishi ,  Hiroyuki Tenmei

IPC分类号： H01L23/538 ,  H01L23/52 ,  H01L23/58

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.

摘要翻译： 本发明包括具有通过正面和背面的电极的半导体元件。 电极形成为包括中空部分的圆柱体，并且应力松弛材料设置在中空部分中，其用于减小在半导体元件和电极之间感应的应力。 应力松弛材料是由树脂材料制成的弹性体。

公开(公告)号：US08334465B2

公开(公告)日：2012-12-18

申请号：US12285222

申请日：2008-09-30

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Hideharu Miyake ,  Shiro Uchiyama ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Hideharu Miyake ,  Shiro Uchiyama ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano

IPC分类号： H05K1/16 ,  H05K1/00 ,  H05K1/03 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/0296 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/2518 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/09 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10674 ,  Y02P70/613

摘要： A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.

摘要翻译： 用于进行三维安装的晶片（或电路板）具有突起20，该突起20设置在用于电连接相互接合的晶片61和62的低熔点金属15中，并且限定相互连接的晶片之间的间隔 61和62，在低熔点金属15熔化时不变形。 通过使用晶片61和62中的至少一个具有突起20来制造晶片61和62的接合结构。在制造的晶片61和62的接合结构中，晶片61和62通过低熔点彼此电连接 点金属15和在低熔点金属15熔化时不会变形的晶片61和62之间的间隔的突起20设置在低熔点金属15中。

公开(公告)号：US20090109641A1

公开(公告)日：2009-04-30

申请号：US12285222

申请日：2008-09-30

申请人： Masakazu Ishino ,  Hiroaki Ikeda ,  Hideharu Miyake ,  Shiro Uchiyama ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano

发明人： Masakazu Ishino ,  Hiroaki Ikeda ,  Hideharu Miyake ,  Shiro Uchiyama ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano

IPC分类号： H05K7/00

CPC分类号： H05K1/0296 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L24/90 ,  H01L25/0657 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/2518 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/09 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10674 ,  Y02P70/613

摘要： A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.

摘要翻译： 用于进行三维安装的晶片（或电路板）具有突起20，该突起20设置在用于电连接相互接合的晶片61和62的低熔点金属15中，并且限定相互连接的晶片之间的间隔 61和62，在低熔点金属15熔化时不变形。 通过使用晶片61和62中的至少一个具有突起20来制造晶片61和62的接合结构。在制造的晶片61和62的接合结构中，晶片61和62通过低熔点彼此电连接 点金属15和在低熔点金属15熔化时不会变形的晶片61和62之间的间隔的突起20设置在低熔点金属15中。

公开(公告)号：US08704352B2

公开(公告)日：2014-04-22

申请号：US12683085

申请日：2010-01-06

申请人： Nae Hisano ,  Shigeo Ohashi ,  Yasuo Osone ,  Yasuhiro Naka ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Hiroaki Ikeda ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama

发明人： Nae Hisano ,  Shigeo Ohashi ,  Yasuo Osone ,  Yasuhiro Naka ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Hiroaki Ikeda ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama

IPC分类号： H01L23/02 ,  H01L23/34

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/473 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

摘要翻译： 半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体 液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

公开(公告)号：US08937390B2

公开(公告)日：2015-01-20

申请号：US14199078

申请日：2014-03-06

申请人： Nae Hisano ,  Shigeo Ohashi ,  Yasuo Osone ,  Yasuhiro Naka ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Hiroaki Ikeda ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama

发明人： Nae Hisano ,  Shigeo Ohashi ,  Yasuo Osone ,  Yasuhiro Naka ,  Hiroyuki Tenmei ,  Kunihiko Nishi ,  Hiroaki Ikeda ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/473 ,  H01L23/34

CPC分类号： H01L24/14 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/473 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

摘要翻译： 半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体 液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

公开(公告)号：US07618847B2

公开(公告)日：2009-11-17

申请号：US12187622

申请日：2008-08-07

申请人： Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano ,  Hiroaki Ikeda ,  Masakazu Ishino

发明人： Hiroyuki Tenmei ,  Kunihiko Nishi ,  Yasuhiro Naka ,  Nae Hisano ,  Hiroaki Ikeda ,  Masakazu Ishino

IPC分类号： H01L21/00

CPC分类号： H01L24/73 ,  H01L21/76898 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/75753 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83871 ,  H01L2224/83907 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/27

摘要： A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

摘要翻译： 提供半导体衬底的接合方法（三维安装），以通过施加的粘合剂顺序地接合形成有耦合凸块的硅晶片的主表面和形成有焊盘的另一个硅晶片的主表面 到至少一个主表面。 然而，由于当焊接在一起时由于凸起和焊盘的位移而存在差的电耦合的问题。 本发明通过进行硅晶片的临时定位来解决这样的问题，通过诸如能够通过硅晶片的x射线的方法确认位置来确定位置，并且将凸块和 一边通过热压而使设置在硅晶片的主表面之间的层间粘合剂硬化。

公开(公告)号：US20050189639A1

公开(公告)日：2005-09-01

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US07119428B2

公开(公告)日：2006-10-10

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L23/22 ,  H01L23/053 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US07573128B2

公开(公告)日：2009-08-11

申请号：US10836098

申请日：2004-04-29

申请人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

发明人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L2224/50 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/01005

摘要： A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.

摘要翻译： 半导体模块包括：各自包括半导体元件的半导体封装，具有连接到半导体元件的布线构件的布线基板和连接到布线构件的外部端子，以及形成在与半导体元件相对的半导体元件的一侧上的第一有机膜 一侧朝向布线基板; 以及安装基板，其上安装有半导体元件。 第一半导体封装和第二半导体封装堆叠。 第二有机膜设置在第一半导体封装的布线基板和第二半导体封装的第一有机膜之间以及安装基板和半导体封装之间。

公开(公告)号：US07477520B2

公开(公告)日：2009-01-13

申请号：US11391450

申请日：2006-03-29

申请人： Masanori Shibamoto ,  Nae Hisano

发明人： Masanori Shibamoto ,  Nae Hisano

IPC分类号： H05K7/20 ,  H01L23/52

CPC分类号： G11C5/00 ,  G11C5/143 ,  H01L23/367 ,  H01L25/105 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K1/181 ,  H01L2924/00

摘要： In a memory module, a plurality of semiconductor memory packages are arranged and mounted on a module board, and a control semiconductor package is disposed in a central region of the arrangement of the semiconductor memory packages, and mounted on the module board. A control semiconductor radiator thermally connected to the control semiconductor package, and a semiconductor memory radiator thermally connected to the plurality of memory packages are disposed without being thermally connected to each other in relation to a direction in which the semiconductor memory packages are arranged.

摘要翻译： 在存储器模块中，多个半导体存储器封装布置并安装在模块板上，并且控制半导体封装设置在半导体存储器封装的布置的中心区域中，并安装在模块板上。 热连接到控制半导体封装的控制半导体散热器和热连接到多个存储器封装的半导体存储器散热器相对于布置半导体存储器封装的方向彼此热连接。