公开(公告)号：US20090134498A1

公开(公告)日：2009-05-28

申请号：US12273590

申请日：2008-11-19

申请人： Hiroaki IKEDA ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama ,  Yasuhiro Naka ,  Nae Hisano ,  Hisashi Tanie ,  Kunihiko Nishi ,  Hiroyuki Tenmei

发明人： Hiroaki IKEDA ,  Masakazu Ishino ,  Hideharu Miyake ,  Shiro Uchiyama ,  Yasuhiro Naka ,  Nae Hisano ,  Hisashi Tanie ,  Kunihiko Nishi ,  Hiroyuki Tenmei

IPC分类号： H01L23/538 ,  H01L23/52 ,  H01L23/58

CPC分类号： H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/2518 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.

摘要翻译： 本发明包括具有通过正面和背面的电极的半导体元件。 电极形成为包括中空部分的圆柱体，并且应力松弛材料设置在中空部分中，其用于减小在半导体元件和电极之间感应的应力。 应力松弛材料是由树脂材料制成的弹性体。

公开(公告)号：US07119428B2

公开(公告)日：2006-10-10

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L23/22 ,  H01L23/053 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US20050189639A1

公开(公告)日：2005-09-01

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US07573128B2

公开(公告)日：2009-08-11

申请号：US10836098

申请日：2004-04-29

申请人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

发明人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L2224/50 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/01005

摘要： A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.

摘要翻译： 半导体模块包括：各自包括半导体元件的半导体封装，具有连接到半导体元件的布线构件的布线基板和连接到布线构件的外部端子，以及形成在与半导体元件相对的半导体元件的一侧上的第一有机膜 一侧朝向布线基板; 以及安装基板，其上安装有半导体元件。 第一半导体封装和第二半导体封装堆叠。 第二有机膜设置在第一半导体封装的布线基板和第二半导体封装的第一有机膜之间以及安装基板和半导体封装之间。

公开(公告)号：US20050001302A1

公开(公告)日：2005-01-06

申请号：US10836098

申请日：2004-04-29

申请人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

发明人： Hisashi Tanie ,  Nae Hisano ,  Koji Hosokawa

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L23/02

CPC分类号： H01L25/105 ,  H01L2224/50 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/01005

摘要： A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.

摘要翻译： 半导体模块包括：各自包括半导体元件的半导体封装，具有连接到半导体元件的布线构件的布线基板和连接到布线构件的外部端子，以及形成在与半导体元件相对的半导体元件的一侧上的第一有机膜 一侧朝向布线基板; 以及安装基板，其上安装有半导体元件。 第一半导体封装和第二半导体封装堆叠。 第二有机膜设置在第一半导体封装的布线基板和第二半导体封装的第一有机膜之间以及安装基板和半导体封装之间。

公开(公告)号：US20130067424A1

公开(公告)日：2013-03-14

申请号：US13593499

申请日：2012-08-23

申请人： Kenichi YAMAMOTO ,  Ryosuke Kimoto ,  Kenya Kawano ,  Hisashi Tanie ,  Yasuhiro Naka

发明人： Kenichi YAMAMOTO ,  Ryosuke Kimoto ,  Kenya Kawano ,  Hisashi Tanie ,  Yasuhiro Naka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G06F17/5018 ,  G06F2217/40 ,  G06F2217/76 ,  G06F2217/80

摘要： A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction.

摘要翻译： 建立了寿命预测精度比现有技术更好的电子设备的寿命预测方法，并且建立了基于上述方法的电子设备的设计方法。 寿命预测通过掺入焊接部分的物理性质的改变和焊料的疲劳寿命的变化来执行，当在高温下放置时发生的变化。 根据热处理温度和热处理时间的关系，确定焊点的物性的变化或焊料的疲劳寿命的变化。 然后将这些变化制定为纳入人生预测。

公开(公告)号：US20090184409A1

公开(公告)日：2009-07-23

申请号：US12357895

申请日：2009-01-22

申请人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US20060216848A1

公开(公告)日：2006-09-28

申请号：US11349913

申请日：2006-02-09

申请人： Hisashi Tanie ,  Takashi Sumigawa ,  Hiroyuki Ohta

发明人： Hisashi Tanie ,  Takashi Sumigawa ,  Hiroyuki Ohta

IPC分类号： H01L21/00

CPC分类号： G01B7/18 ,  G01L1/2293

摘要： A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.

公开(公告)号：US20050230829A1

公开(公告)日：2005-10-20

申请号：US11081658

申请日：2005-03-17

申请人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

发明人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

IPC分类号： H05K1/02 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K1/111 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09281 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.

摘要翻译： 半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。 在封装基板5上形成有多个列，其中布置有多个焊盘8。 构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。 互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线 封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

公开(公告)号：US20050230824A1

公开(公告)日：2005-10-20

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。