公开(公告)号：US5066355A

公开(公告)日：1991-11-19

申请号：US438290

申请日：1989-11-16

申请人： Masanobu Miyao ,  Kiyokazu Nakagawa ,  Kiyonori Ohyu ,  Eiichi Murakami ,  Takashi Ohshima

发明人： Masanobu Miyao ,  Kiyokazu Nakagawa ,  Kiyonori Ohyu ,  Eiichi Murakami ,  Takashi Ohshima

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L21/28518 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/02658 ,  Y10S438/933 ,  Y10S438/938

摘要： A method of producing a hetero structure, including the steps of depositing hydrogen atoms or halogen atoms onto a surface of a first single crystal layer formed of semiconductor or metal silicide, and forming a second single crystal layer on the first single crystal layer by hetero epitaxial growth, the second single crystal layer being formed of semiconductor or metal silicide different from the material of the first single crystal layer, wherein both of the steps are continuously conducted without taking the hetero structure out of a producing device. Further, the number of the hydrogen atoms or the halogen atoms to be deposited is equal to or in the range of .+-.50% with reference to the number of dangling bonds existing in a hetero interface between the first single crystal layer and the second single crystal layer, so that the lattice defects in the hetero interface can be reduced.

公开(公告)号：US5241197A

公开(公告)日：1993-08-31

申请号：US759772

申请日：1991-09-13

申请人： Eiichi Murakami ,  Kiyokazu Nakagawa ,  Takashi Ohshima ,  Hiroyuki Eto ,  Masanobu Miyao

发明人： Eiichi Murakami ,  Kiyokazu Nakagawa ,  Takashi Ohshima ,  Hiroyuki Eto ,  Masanobu Miyao

IPC分类号： H01L27/085 ,  H01L29/165 ,  H01L29/737 ,  H01L29/778 ,  H01L29/80

CPC分类号： H01L29/7378 ,  H01L27/085 ,  H01L29/165 ,  H01L29/7373 ,  H01L29/7782 ,  H01L29/802

摘要： A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.

摘要翻译： 可以通过利用应变锗层中的载流子迁移率大的事实来形成具有高载流子迁移率且适于高速操作的晶体管。 在锗层下方设置应变控制层，以在锗层上施加压缩应变，并且使用预定范围内的应变控制层的组成以确定地产生压缩应变。

公开(公告)号：US4808546A

公开(公告)日：1989-02-28

申请号：US9476

申请日：1987-02-02

申请人： Masahiro Moniwa ,  Masanobu Miyao ,  Shoji Shukuri ,  Eiichi Murakami ,  Terunori Warabisako ,  Masao Tamura ,  Nobuyoshi Natsuaki ,  Kiyonori Ohyu ,  Tadashi Suzuki ,  Yuuichi Madokoro ,  Yasuo Wada

发明人： Masahiro Moniwa ,  Masanobu Miyao ,  Shoji Shukuri ,  Eiichi Murakami ,  Terunori Warabisako ,  Masao Tamura ,  Nobuyoshi Natsuaki ,  Kiyonori Ohyu ,  Tadashi Suzuki ,  Yuuichi Madokoro ,  Yasuo Wada

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/265 ,  H01L21/26

CPC分类号： H01L29/66772 ,  H01L21/2022 ,  H01L21/76248 ,  Y10S148/003 ,  Y10S148/048 ,  Y10S148/09 ,  Y10S148/154

摘要： Of an amorphous Si film, a region to be formed into a lowly doped region such as the channel region of an MOS transistor is covered with a mask and an uncovered region is doped with an impurity. After this, the amorphous Si film is annealed and turned to signal crystal through solid phase epitaxial growth, and the mask itself is used as the electrode of a semiconductor device. By this impurity doping, a large-sized single-crystal Si film can be formed, and the impurity doping can be conducted in self-alignment with the electrode formation to produce a highly integrated semiconductor circuit.

摘要翻译： 在非晶Si膜中，用掩模覆盖要形成诸如MOS晶体管的沟道区域的低掺杂区域的区域，并且未覆盖区域掺杂有杂质。 之后，通过固相外延生长使非晶Si膜退火并转向信号晶体，并且将掩模本身用作半导体器件的电极。 通过这种杂质掺杂，可以形成大尺寸的单晶Si膜，并且杂质掺杂可以与电极形成自对准，以产生高度集成的半导体电路。

公开(公告)号：US4984048A

公开(公告)日：1991-01-08

申请号：US216536

申请日：1988-07-08

申请人： Kazuhiko Sagara ,  Tokuo Kure ,  Eiichi Murakami ,  Tohru Nakamura ,  Masanobu Miyao ,  Masao Kondo ,  Akitoshi Ishizaka ,  Yoichi Tamaki

发明人： Kazuhiko Sagara ,  Tokuo Kure ,  Eiichi Murakami ,  Tohru Nakamura ,  Masanobu Miyao ,  Masao Kondo ,  Akitoshi Ishizaka ,  Yoichi Tamaki

IPC分类号： H01L21/74 ,  H01L21/763 ,  H01L29/06 ,  H01L29/417 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/0649 ,  H01L21/743 ,  H01L21/763 ,  H01L29/41716 ,  H01L29/7325 ,  H01L29/7327 ,  H01L29/7378

摘要： Polycrystalline silicon which is provided within a trench for isolating a plurality of bipolar transistors from each other is electrically connected to the collector of one of the bipolar transistor. Since the trench for isolation can also be used to lead out the collector electrode, the required area is minimized. Thus, the arrangement is effective in creasing the integration density.

摘要翻译： 设置在用于将多个双极晶体管彼此隔离的沟槽内的多晶硅电连接到双极晶体管之一的集电极。 由于用于隔离的沟槽也可以用于引出集电极，因此所需的面积被最小化。 因此，这种布置在增加集成密度方面是有效的。

公开(公告)号：US5689494A

公开(公告)日：1997-11-18

申请号：US441700

申请日：1995-05-15

申请人： Masakazu Ichikawa ,  Shigeyuki Hosoki ,  Fumihiko Uchida ,  Shigeo Kato ,  Yoshihisa Fujisaki ,  Sumiko Fujisaki ,  Atsushi Kikugawa ,  Ryo Imura ,  Hajime Aoi ,  Kiyokazu Nakagawa ,  Eiichi Murakami

发明人： Masakazu Ichikawa ,  Shigeyuki Hosoki ,  Fumihiko Uchida ,  Shigeo Kato ,  Yoshihisa Fujisaki ,  Sumiko Fujisaki ,  Atsushi Kikugawa ,  Ryo Imura ,  Hajime Aoi ,  Kiyokazu Nakagawa ,  Eiichi Murakami

IPC分类号： B82B3/00 ,  G01Q60/00 ,  G01Q80/00 ,  G01Q90/00 ,  G11B9/00 ,  G11B11/08 ,  G11B33/14 ,  H01J37/30 ,  H01J37/305 ,  H01J37/317 ,  G11B7/00

CPC分类号： G11B9/1436 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11B11/08 ,  G11B33/14 ,  G11B9/00 ,  G11B9/14 ,  G11B9/1418 ,  G11B9/1445 ,  G11B9/1463 ,  G11B9/1472 ,  H01J37/3056 ,  H01J37/3174 ,  G01Q80/00 ,  H01J2237/31738 ,  H01J2237/31759 ,  Y10S977/856 ,  Y10S977/947

摘要： A fine-fabrication method of solid surfaces relates to a new surface fabrication method allows a solid-device surface to be fabricated at an atomic scale so as to produce an ultra-fine device or a device for recording information at an ultra-high density. A probe is installed with a tip thereof facing to the surface of a specimen to undergo fabrication. A voltage for forming an electric field is applied between the probe and the specimen. The electric field is large enough to field-evaporate atoms constituting the specimen or the probe; the electric field field-evaporates atoms constituting the specimen, removing them from the surface of the specimen; and as another alternative, the electric field field-evaporates atoms constituting the probe, depositing them on the surface of the specimen. Further, in another surface atom fabrication method, while the surface of a specimen is observed at an atomic scale using a surface observation technique by means of a scanning tunnelling microscope, a pulsative voltage large enough for the field evaporation of atoms described above is applied between the probe and the specimen at any arbitrary desired positions on the surface of the specimen; and the pulsative voltage field-evaporates and, hence, eliminates atoms one by one from the surface of the specimen.

摘要翻译： 固体表面的精细制造方法涉及新的表面制造方法，可以以原子尺度制造固体器件表面，以便产生超细的器件或以超高密度记录信息的器件。 安装探针，其尖端面向样品的表面进行制造。 在探针和样品之间施加用于形成电场的电压。 电场足够大以使构成样品或探针的原子挥发蒸发; 电场场蒸发构成样品的原子，将其从试样的表面除去; 并且作为另一种替代方案，电场场蒸发构成探针的原子，将它们沉积在样品的表面上。 此外，在另一表面原子制造方法中，利用扫描隧道显微镜利用表面观察技术以原子尺度观察试样的表面，在上述原子的场蒸发之前足够大的脉动电压被施加在 探针和样品在样品表面上任意任意的位置; 并且脉动电压场蒸发，因此从样品的表面逐个消除原子。

公开(公告)号：US5416331A

公开(公告)日：1995-05-16

申请号：US934672

申请日：1992-09-11

申请人： Masakazu Ichikawa ,  Shigeyuki Hosoki ,  Fumihiko Uchida ,  Shigeo Kato ,  Yoshihisa Fujisaki ,  Sumiko Fujisaki ,  Atsushi Kikugawa ,  Ryo Imura ,  Hajime Aoi ,  Kiyokazu Nakagawa ,  Eiichi Murakami

发明人： Masakazu Ichikawa ,  Shigeyuki Hosoki ,  Fumihiko Uchida ,  Shigeo Kato ,  Yoshihisa Fujisaki ,  Sumiko Fujisaki ,  Atsushi Kikugawa ,  Ryo Imura ,  Hajime Aoi ,  Kiyokazu Nakagawa ,  Eiichi Murakami

IPC分类号： B82B3/00 ,  G01Q60/00 ,  G01Q80/00 ,  G01Q90/00 ,  G11B9/00 ,  G11B11/08 ,  G11B33/14 ,  H01J37/30 ,  H01J37/305 ,  H01J37/317

CPC分类号： G11B9/1436 ,  B82B3/00 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11B11/08 ,  G11B33/14 ,  G11B9/00 ,  G11B9/14 ,  G11B9/1418 ,  G11B9/1445 ,  G11B9/1463 ,  G11B9/1472 ,  H01J37/3056 ,  H01J37/3174 ,  G01Q80/00 ,  H01J2237/31738 ,  H01J2237/31759 ,  Y10S977/856 ,  Y10S977/947

摘要： A fine-fabrication method of solid surfaces relates to a new surface fabrication method allows a solid-device surface to be fabricated at an atomic scale so as to produce an ultra-fine device or a device for recording information at an ultra-high density. A probe is installed with a tip thereof facing to the surface of a specimen to undergo fabrication. A voltage for forming an electric field is applied between the probe and the specimen. The electric field is large enough to field-evaporate atoms constituting the specimen or the probe; the electric field field-evaporates atoms constituting the specimen, removing them from the surface of the specimen; and as another alternative, the electric field field-evaporates atoms constituting the probe, depositing them on the surface of the specimen. Further, in another surface atom fabrication method, while the surface of a specimen is observed at an atomic scale using a surface observation technique by means of a scanning tunnelling microscope, a pulsative voltage large enough for the field evaporation of atoms described above is applied between the probe and the specimen at any arbitrary desired positions on the surface of the specimen; and the pulsative voltage field-evaporates and, hence, eliminates atoms one by one from the surface of the specimen.

摘要翻译： PCT No.PCT / JP92 / 00015 Sec。 371日期：1992年9月11日 102（e）1992年9月11日PCT PCT 1991年1月10日PCT公布。 公开号WO92 / 12528 日期：1992年7月23日。固体表面的精细制造方法涉及新的表面制造方法，可以以原子尺度制造固体器件表面，以便制造超精细器件或用于记录信息的器件 超高密度。 安装探针，其尖端面向样品的表面进行制造。 在探针和样品之间施加用于形成电场的电压。 电场足够大以使构成样品或探针的原子挥发蒸发; 电场场蒸发构成样品的原子，将其从试样的表面除去; 并且作为另一种替代方案，电场场蒸发构成探针的原子，将它们沉积在样品的表面上。 此外，在另一表面原子制造方法中，利用扫描隧道显微镜利用表面观察技术以原子尺度观察试样的表面，在上述原子的场蒸发之前足够大的脉动电压被施加在 探针和样品在样品表面上任意任意的位置; 并且脉动电压场蒸发，因此从样品的表面逐个消除原子。

公开(公告)号：US5338942A

公开(公告)日：1994-08-16

申请号：US90

申请日：1993-01-04

申请人： Akio Nishida ,  Eiichi Murakami ,  Kiyokazu Nakagawa

发明人： Akio Nishida ,  Eiichi Murakami ,  Kiyokazu Nakagawa

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L21/331 ,  H01L21/338 ,  H01L29/06 ,  H01L29/165 ,  H01L29/267 ,  H01L29/73 ,  H01L29/737 ,  H01L29/778 ,  H01L29/812 ,  H01L29/04

CPC分类号： H01L29/267 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L29/0657 ,  H01L29/165

摘要： A semiconductor device comprising a semiconductor crystalline substrate having projections each thereof having an area of 0.01 .mu.m.sup.2 to 4 .mu.m.sup.2 or stripe projections each thereof having a width of 0.01 .mu.m to 1 .mu.m and semiconductor crystalline layers formed on the projections, each of the layers having lattice constants different from those of the semiconductor crystalline substrate preferably by 0.5% or more. The semiconductor device is free of dislocations and thermally stable. The semiconductor device can be fabricated by performing such processes as forming projections on the substrate and forming semiconductor crystalline layers on the projections by molecular beam epitaxy.

摘要翻译： 一种半导体器件，包括具有其面积为0.01μm至4μm的突起的半导体晶体基板或其宽度为0.01μm至1μm的条形突起，以及形成在所述突起上的半导体晶体层 这些层的晶格常数与半导体结晶基板的晶格常数不同，优选为0.5％以上。 半导体器件没有位错并且热稳定。 半导体器件可以通过进行诸如在衬底上形成突起并通过分子束外延在突起上形成半导体晶体层的工艺来制造。

公开(公告)号：US08544344B2

公开(公告)日：2013-10-01

申请号：US13296365

申请日：2011-11-15

申请人： Eiichi Murakami

发明人： Eiichi Murakami

IPC分类号： G01F1/66

CPC分类号： G01F1/662 ,  G01F15/14

摘要： First and second piezoelectric transducers 2 and 3 are fixed to a tubular main body 1 via first and second fitting bases 4 and 5. On front and rear surfaces of an end portion of each of the first and second piezoelectric transducers 2 and 3 are provided first and second electrodes 6 and 7. When the tubular main body 1 is secured to a circuit box, each of the end portions of the first and second piezoelectric transducers 2 and 3 is inserted between first and second contact members provided on the circuit box such that the first and second electrodes 6 and 7 are electrically connected to the first and second contact members, respectively to connect the first and second piezoelectric transducers 2 and 3 to the circuit box by one touch operation.

摘要翻译： 第一和第二压电换能器2和3经由第一和第二配件基座4和5固定到管状主体1.在第一和第二压电换能器2和3中的每一个的端部的前表面和后表面被设置为第一 和第二电极6和7.当管状主体1固定到电路箱时，第一和第二压电换能器2和3的每个端部插入设置在电路箱上的第一和第二接触构件之间，使得 第一和第二电极6和7分别电连接到第一和第二接触构件，以通过一次触摸操作将第一和第二压电换能器2和3连接到电路箱。

公开(公告)号：US20060111805A1

公开(公告)日：2006-05-25

申请号：US11320778

申请日：2005-12-30

申请人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

发明人： Natsuki Yokoyama ,  Yoshifumi Kawamoto ,  Eiichi Murakami ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Yoshio Kawamura

IPC分类号： G06F19/00

CPC分类号： C23C14/568 ,  C23C16/54 ,  G05B19/41865 ,  G05B2219/45031 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67173 ,  H01L21/67184 ,  H01L21/67276 ,  H01L21/67727 ,  H01L21/67745 ,  Y02P90/14 ,  Y02P90/20 ,  Y02P90/28 ,  Y10S414/135 ,  Y10S414/137 ,  Y10S438/908 ,  Y10T29/41

摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.

摘要翻译： 一种用于系统的制造方法，包括通过机构间运送器彼此连接的多个处理装置。 半导体水在处理装置中进行处理，并以不同的时间间隔被传送到规定的处理装置，时间间隔设定为单位时间间隔的N倍。 由于制造系统包括以与单位时间相关的时间间隔周期性地控制的处理装置和装置间运送器，所以与单位时间相关的间隔，可以有效地进行多个作品的调度以增强优化级别 ，从而提高生产率。

公开(公告)号：US5562800A

公开(公告)日：1996-10-08

申请号：US308442

申请日：1994-09-19

申请人： Yoshio Kawamura ,  Yoshifumi Kawamoto ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Natsuki Yokoyama ,  Eiichi Murakami ,  Yoshinori Nakayama ,  Eiichi Seya

发明人： Yoshio Kawamura ,  Yoshifumi Kawamoto ,  Fumihiko Uchida ,  Kenichi Mizuishi ,  Natsuki Yokoyama ,  Eiichi Murakami ,  Yoshinori Nakayama ,  Eiichi Seya

IPC分类号： B65G49/00 ,  B65G49/07 ,  H01L21/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/677

CPC分类号： H01L21/67748 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67742 ,  Y10S414/135 ,  Y10S414/139 ,  Y10S438/935

摘要： A wafer transport method includes the steps of preparing a semiconductor process equipment having a transport chamber and a process chamber. An interface means connects the transport chamber to the process chamber. A transport means transports a semiconductor wafer from the transport chamber to the process chamber by way of the interface means. The transport means mounting a substrate is inserted into a communicating corridor including a supply means and an exhaust means. The substrate is transported while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor. Thus, the substrate is transported at a high throughput without contamination of the substrate while keeping the different atmospheric conditions for the transport chamber and the process chamber, thereby manufacturing a semiconductor device with high performance capabilities.

摘要翻译： 晶片输送方法包括准备具有输送室和处理室的半导体工艺设备的步骤。 接口装置将输送室连接到处理室。 传送装置通过接口装置将半导体晶片从传送室传送到处理室。 安装基板的输送装置被插入到包括供给装置和排气装置的通信走廊中。 通过根据由输送装置和通信走廊之间的间隙形成的电导部分的位置依次控制供给切断装置，排气关闭装置和通信切断装置，在进行供给和排出的同时运送基板。 因此，在保持输送室和处理室的不同大气条件的同时，以高通量输送基板而不污染基板，从而制造具有高性能的半导体器件。