公开(公告)号：US06509277B1

公开(公告)日：2003-01-21

申请号：US09664381

申请日：2000-09-18

申请人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

发明人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

IPC分类号： H01L21302

CPC分类号： H01L21/3124 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10894

摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode 9 of a MISFET (Qs, Qn, Qp). A polysilazan SOG film 57 not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

摘要翻译： 使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET（Qs，Qn，Qp）的栅极9上的平坦化绝缘膜。 不进行这种热处理的聚硅氮烷SOG膜57被用作布置在上部布线层（54,55,56,62,63）之间的层间绝缘膜。

公开(公告)号：US06833331B2

公开(公告)日：2004-12-21

申请号：US10303935

申请日：2002-11-26

申请人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

发明人： Masayoshi Saito ,  Katsuhiko Hotta ,  Masayoshi Hirasawa ,  Masayuki Kojima ,  Hiroyuki Uchiyama ,  Hiroyuki Maruyama ,  Takuya Fukuda

IPC分类号： H01L2131

CPC分类号： H01L21/3124 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10894

摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

摘要翻译： 使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET的栅极（9;参见图31和32）上的平坦化绝缘膜） （Qs，Qn，Qp）将不进行这种热处理的聚硅氮烷SOG膜（57）用作布置在上布线层（54,55,56,62,63）中的层间绝缘膜。

公开(公告)号：US5264712A

公开(公告)日：1993-11-23

申请号：US881314

申请日：1992-05-07

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L21/308 ,  H01L29/66

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US5917211A

公开(公告)日：1999-06-29

申请号：US979543

申请日：1997-11-25

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L21/8234 ,  H01L27/105 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  H01L21/823425

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

摘要翻译： 一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。 当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

公开(公告)号：US5734188A

公开(公告)日：1998-03-31

申请号：US674185

申请日：1996-07-01

申请人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

发明人： Jun Murata ,  Yoshitaka Tadaki ,  Hiroko Kaneko ,  Toshihiro Sekiguchi ,  Hiroyuki Uchiyama ,  Hisashi Nakamura ,  Toshio Maeda ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Ogishima ,  Masaki Nagao ,  Michimasa Funabashi ,  Yasuo Kiguchi ,  Masayuki Kojima ,  Atsuyoshi Koike ,  Hiroyuki Miyazawa ,  Masato Sadaoka ,  Kazuya Kadota ,  Tadashi Chikahara ,  Kazuo Nojiri ,  Yutaka Kobayashi

IPC分类号： H01L27/105 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L3/119

CPC分类号： H01L27/105

摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

公开(公告)号：US20100132392A1

公开(公告)日：2010-06-03

申请号：US12095107

申请日：2006-11-26

申请人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

发明人： Masanao Yasutomi ,  Masayuki Kojima ,  Masuzou Takahashi ,  Toshihiro Wakamatsu

IPC分类号： F25D21/14 ,  F25D17/06

CPC分类号： F24F1/0007 ,  F24F1/0025 ,  F24F13/222

摘要： Grooves are formed on a back surface 22 of a tongue part 21 of a rear plate 3 which surface does not guide a flow of air.

摘要翻译： 凹槽形成在后板3的舌部21的后表面22上，该表面不引导空气流。

公开(公告)号：US07081649B2

公开(公告)日：2006-07-25

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn 1和Q n 2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp 1中，形成高密度N型半导体区域16和16b，以及 高密度P型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06838388B2

公开(公告)日：2005-01-04

申请号：US09893577

申请日：2001-06-29

申请人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

发明人： Masahiro Tadokoro ,  Masahiro Shioya ,  Masayuki Kojima ,  Takenobu Ikeda

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10855 ,  H01L27/10888

摘要： A fabrication method of a semiconductor integrated circuit device comprises, in an SAC process or HARC process, subjecting a semiconductor substrate to plasma etching to make contact holes in an oxide film made of a silicon oxide film formed on the semiconductor substrate. For improving the ease-in-etching property of the silicon oxide film and selectivity to a nitride film, a residence time of an etching gas within a chamber is so set as to be in a range where selectivity to an insulating film made of silicon nitride is improved by using etching conditions of a low pressure and a large flow rate of the etching gas of C5H8/O2/Ar.

公开(公告)号：US06743673B2

公开(公告)日：2004-06-01

申请号：US10145810

申请日：2002-05-16

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06537415B2

公开(公告)日：2003-03-25

申请号：US09942707

申请日：2001-08-31

申请人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

发明人： Masayuki Kojima ,  Yoshimi Torii ,  Michimasa Hunabashi ,  Kazuyuki Suko ,  Takashi Yamada ,  Keizo Kuroiwa ,  Kazuo Nojiri ,  Yoshinao Kawasaki ,  Yoshiaki Sato ,  Ryooji Fukuyama ,  Hironobu Kawahara

IPC分类号： H01L213065

CPC分类号： H01L21/32136 ,  C23F4/00 ,  H01J37/185 ,  H01L21/67017 ,  H01L21/67028 ,  H01L21/67069 ,  H01L21/67161 ,  H01L21/67207 ,  H01L21/67745 ,  H01L21/67751

摘要： Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.