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1.发明授权
公开(公告)号：US5872696A
公开(公告)日：1999-02-16
申请号：US826980
申请日：1997-04-09
摘要： Novel structures for capacitors which are capable of withstanding heat treatments to at least 400.degree. C. while providing low defect densities and low electrical series resistance in its electrodes are disclosed. In one embodiment of the present invention, a capacitor structure includes a bottom capacitor electrode formed of a first sub-layer of aluminum, a second sub-layer of tantalum nitride, and a third sub-layer of tantalum. The capacitor structure further includes a sputtered dielectric layer of tantalum pentoxide over the tantalum sub-layer of the bottom electrode. The resulting structure is anodized such that the underlying tantalum layer is fully anodized, and preferably such that a portion of the tantalum nitride layer is converted to a tantalum oxy-nitride. The tantalum nitride layer was discovered by the inventors to act as a good high temperature diffusion barrier for the aluminum, preventing the aluminum from migrating into the anodized tantalum pentoxide layer under high temperature processing conditions, where it would chemically reduce the tantalum atoms in the tantalum pentoxide layer and introduce conductive paths of tantalum in the dielectric (tantalum pentoxide) layer. The aluminum layer provides good electrical conductivity for the bottom electrode, and is anodized to fill any pinhole defects in the layers formed above it, thereby increasing manufacturing yields.
摘要翻译： 公开了一种电容器的新型结构，其能够耐热处理至少400℃，同时在其电极中提供低缺陷密度和低电串联电阻。 在本发明的一个实施例中，电容器结构包括由铝的第一子层，氮化钽的第二子层和钽的第三子层形成的底部电容器电极。 电容器结构还包括在底部电极的钽子层上的五氧化二钽的溅射介电层。 所得到的结构被阳极氧化，使得下面的钽层被完全阳极氧化，并且优选地使得一部分氮化钽层转化为氮氧化钽。 本发明人发现氮化钽层用作铝的良好的高温扩散阻挡层，防止铝在高温加工条件下迁移到阳极氧化的五氧化二钽层中，其中它将化学还原钽中的钽原子 并在介电（五氧化二钽）层中引入钽的导电路径。 铝层为底部电极提供良好的导电性，并被阳极氧化以填充其上形成的层中的任何针孔缺陷，从而提高制造产量。
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2.发明授权公开(公告)号：US06226171B1
公开(公告)日：2001-05-01
申请号：US09227239
申请日：1999-01-08
申请人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
发明人： Solomon I. Beilin , William T. Chou , Michael G. Lee , David Dung Ngo , Michael G. Peters , James J. Roman , Yasuhito Takahashi
IPC分类号： H01G4228
CPC分类号： H01L23/50 , H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/056 , H05K1/162 , H05K3/045 , H05K3/388 , H05K3/44 , H05K2201/0154 , H05K2201/0195 , H05K2201/09481 , H05K2201/09509 , H05K2201/09554 , H05K2203/0315 , H01L2924/00
摘要： Several inventive features for increasing the yield of substrate capacitors are disclosed. The inventive features relating to selective placement of insulating layers and patches around selected areas of the capacitor's main dielectric layer. These insulating layers and defects prevent certain manufacturing processing steps from creating pin-hole defects in the main dielectric layer. The inventive features are suitable for any type of material for the main dielectric layer, and are particularly suited to anodized dielectric layers.
摘要翻译： 公开了用于增加基板电容器的产量的几个发明特征。 本发明的特征涉及在电容器的主介电层的选定区域周围选择性地放置绝缘层和贴片。 这些绝缘层和缺陷防止某些制造处理步骤在主介电层中产生针孔缺陷。 本发明的特征适合于用于主介电层的任何类型的材料，并且特别适用于阳极化电介质层。
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公开(公告)号：US5454161A
公开(公告)日：1995-10-03
申请号：US54899
申请日：1993-04-29
CPC分类号： H01L21/486 , H01L23/49827 , H01L2224/16 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , Y10T29/49124 , Y10T29/49144 , Y10T29/49165
摘要： A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify. The support structure is removed and the through-hole interconnector, comprising the metalized vias and the second dielectric material, is lapped and polished to predetermined manufacturing dimensions and tolerances.
摘要翻译： 具有高纵横比通孔的高密度通孔互连通过在先前的介电层上依次形成电介质材料层来形成。 在形成每一层之后，通过每个层蚀刻多个通孔，并用与其将连接的电介质层和集成电路的热膨胀系数匹配的导热材料填充或金属化。 优选地，重复形成电介质层，形成通孔和使通孔金属化的工艺，直到金属化通孔具有在6至10范围内的纵横比。支撑结构被构造成与金属化的 电介质材料被去除时的通孔。 将具有期望的机械和电学性能的第二介电材料倒入支撑结构中以填充金属化通孔之间的空间并使其固化。 移除支撑结构，并且将包括金属化通孔和第二介电材料的通孔互连器重叠并抛光至预定的制造尺寸和公差。
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公开(公告)号：US5323520A
公开(公告)日：1994-06-28
申请号：US054910
申请日：1993-04-29
CPC分类号： H01G4/232 , H01G4/306 , H05K1/162 , H01L2224/16145 , H01L2224/16225 , H01L2924/1305 , H05K1/112 , H05K2201/0317 , H05K2201/09309 , H05K2203/0315 , Y10T29/435 , Y10T29/49165
摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要翻译： 通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。 将背面金属化层序列施加到基底基板的背面。 底部接触层序列被施加到基底基板的前侧表面。 形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。 去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。 在绝缘层的表面形成接地金属化馈通和功率金属化馈通。 顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。 背面接地端子和背面电源端子形成在基底基板的背面。
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公开(公告)号：US5854534A
公开(公告)日：1998-12-29
申请号：US559369
申请日：1995-11-16
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01L23/52 , H01L23/04 , H01L23/053 , H01L23/34
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed though rigid segments and signals are routed though a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段传送，信号通过薄膜柔性连接器布线，该连接器从插入器基板的上表面延伸到下表面。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。
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公开(公告)号：US5544017A
公开(公告)日：1996-08-06
申请号：US277163
申请日：1994-07-19
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou V. Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译： 公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。 衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。 在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。 这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。 不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。 优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。
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公开(公告)号：US5419038A
公开(公告)日：1995-05-30
申请号：US78461
申请日：1993-06-17
申请人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
发明人： Wen-chou V. Wang , Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy
CPC分类号： H05K3/4691 , H05K2201/0394 , H05K3/002 , H05K3/0023 , H05K3/0041 , H05K3/467 , Y10T29/49124 , Y10T29/49126 , Y10T29/49165
摘要： A three dimensional thin-film interconnector is fabricated by depositing a dielectric layer onto the surface of a substrate, depositing a layer of conductive material onto the dielectric layer to form a signal plane, depositing a dielectric layer onto the surface of the signal plane, forming a plurality of through holes in the dielectric layer that extend to the signal plane, and filling the through holes with an electrically conductive material to form vias. The sequence of forming a signal plane, depositing a dielectric layer, forming a plurality of through holes, and filling the through holes is repeated until a predetermined number of signal planes and a predetermined arrangement of vias are obtained. The through holes are formed at locations in the dielectric layers corresponding to both predetermined electrical connections and the vias in a preceding dielectric layer. The signal planes are formed at different locations on the substrate. The sequence of signal planes and dielectric layers at the same location on the substrate form a signal plane set which defines a connector. Contact pads are deposited onto the surface of a final dielectric layer and electrically connect with each via. Wires are used to electrically connect the contact pads of one connector to corresponding contact pads of another connector. A portion of the substrate and dielectric layers not comprising a signal plane set is removed, forming electrical connectors flexibly attached by the plurality of wires.
摘要翻译： 通过在衬底的表面上沉积介电层来制造三维薄膜互连器，在电介质层上沉积导电材料层以形成信号平面，在信号面的表面上沉积电介质层，形成 电介质层中的多个通孔延伸到信号平面，并用导电材料填充通孔以形成通孔。 重复形成信号平面，沉积介电层，形成多个通孔和填充通孔的顺序，直到获得预定数量的信号面和通孔的预定布置。 通孔形成在电介质层中对应于先前电介质层中的预定电连接和通路两者的位置处。 信号面形成在基板上的不同位置。 基板上相同位置处的信号平面和电介质层的顺序形成了限定连接器的信号平面组。 接触焊盘沉积在最终电介质层的表面上并与每个通孔电连接。 电线用于将一个连接器的接触焊盘电连接到另一个连接器的相应接触焊盘。 除去不包括信号平面组的衬底和电介质层的一部分，形成由多个电线柔性附接的电连接器。
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公开(公告)号：US6102710A
公开(公告)日：2000-08-15
申请号：US70493
申请日：1998-04-30
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-chou Vincent Wang , Larry L. Moresco , Teruo Murase
IPC分类号： H01L21/48 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01R12/00
CPC分类号： H05K1/144 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/5387 , H01L23/66 , H01L25/0652 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2924/3011
摘要： An interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, are shown. The interposer substrate comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other. Power supply is routed through rigid segments and signals are routed through a thin film flexible connector that runs from the upper surface of the interposer substrate to the lower surface. Bypass capacitance is incorporated into the interposer substrate and connected to the power supply so that it is positioned very close to the integrated circuit chip. The interposer may be fabricated by forming a multilayered thin film structure including the signal paths over a rigid substrate having vias formed therein, removing the central portion of the substrate leaving the two end segments, and folding and joining the end segments such that the vias are connected. In another embodiment of the invention, a separate power plate is provided for carrying the power lines. Portions of the power plate, with a multilayered thin film structure thereon, are cut and folded to form interposers. Methods of making single-chip interposers are also disclosed.
摘要翻译： 示出了用于将集成电路芯片安装到基板的插入器基板及其制造方法。 插入器基板包括彼此基本隔离的电源路径和受控阻抗信号路径。 电源通过刚性段布线，信号通过从内插器基板的上表面延伸到下表面的薄膜柔性连接器。 旁路电容被并入到插入器基板中并且连接到电源，使得其非常靠近集成电路芯片。 可以通过在其上形成有通孔的刚性基板上形成包括信号路径的多层薄膜结构来制造插入件，去除离开两端段的基板的中心部分，以及折叠和连接端部段，使得通孔为 连接的。 在本发明的另一实施例中，提供了用于承载电源线的单独的功率板。 在其上具有多层薄膜结构的功率板的部分被切割和折叠以形成插入件。 还公开了制造单芯片插入件的方法。
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9.发明授权Methods of etching through wafers and substrates with a composite etch stop layer 失效用复合蚀刻停止层蚀刻晶片和衬底的方法
公开(公告)号：US5891354A
公开(公告)日：1999-04-06
申请号：US687723
申请日：1996-07-26
申请人： Michael G. Lee , Solomon I. Beilin , William T. Chou , Michael G. Peters , Wen-chou Vincent Wang
发明人： Michael G. Lee , Solomon I. Beilin , William T. Chou , Michael G. Peters , Wen-chou Vincent Wang
IPC分类号： H01L21/78 , H01L23/482 , H05K3/00 , B44C1/22 , H05K3/06
CPC分类号： H01L21/30604 , H01L21/78 , H01L23/4822 , H01L24/01 , H01L2924/01029 , H05K3/0017
摘要： Methods of wet etching through a silicon substrate using composite etch-stop layers are disclosed. In one embodiment, the composite etch stop comprises a layer of silicon dioxide and a layer of polyimide.
摘要翻译： 公开了通过使用复合蚀刻停止层的硅衬底进行湿蚀刻的方法。 在一个实施例中，复合蚀刻停止件包括二氧化硅层和聚酰亚胺层。
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公开(公告)号：US5778529A
公开(公告)日：1998-07-14
申请号：US651479
申请日：1996-05-22
申请人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
发明人： Solomon I. Beilin , William T. Chou , David Kudzuma , Michael G. Lee , Teruo Murase , Michael G. Peters , James J. Roman , Som S. Swamy , Wen-Chou Vincent Wang
IPC分类号： H01L21/48 , H01L23/473 , H01L23/498 , H01L23/538 , H01L23/66 , H01L25/065 , H05K1/14 , H01K3/10 , H05K3/10
CPC分类号： H01L21/486 , H01L21/4857 , H01L23/473 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5385 , H01L23/66 , H01L25/0652 , H05K1/144 , H01L2224/16 , H01L2924/00013 , H01L2924/01019 , H01L2924/01078 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204
摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.
摘要翻译： 公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。 衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。 在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。 这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。 不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。 优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。
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