公开(公告)号：US5778529A

公开(公告)日：1998-07-14

申请号：US651479

申请日：1996-05-22

申请人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Teruo Murase ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-Chou Vincent Wang

发明人： Solomon I. Beilin ,  William T. Chou ,  David Kudzuma ,  Michael G. Lee ,  Teruo Murase ,  Michael G. Peters ,  James J. Roman ,  Som S. Swamy ,  Wen-Chou Vincent Wang

IPC分类号： H01L21/48 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H01K3/10 ,  H05K3/10

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/473 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0652 ,  H05K1/144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A multichip module substrate for use in a three-dimensional multichip module, and methods of making the same, are disclosed. The substrate comprises a thin film structure, for routing signals to and from integrated circuit chips, formed over a rigid support base. Apertures are formed in the support base exposing the underside of the thin film structure, thereby allowing high density connectors to be mounted on both surfaces of the thin film structure, greatly enhancing the ability to communicate signals between adjacent substrates in the chip module. This avoids the need to route the signals either through the rigid support base or to the edges of the thin film structure. Power and ground, which do not require a high connection density, are routed in low impedance paths through the support base. Preferably, the thin film structure is made of alternating layers of patterned metal, such as copper, and a low dielectric organic polymer, such as a polyimide.

摘要翻译： 公开了一种用于三维多芯片模块的多芯片模块基板及其制造方法。 衬底包括薄膜结构，用于将信号路由到集成电路芯片上并从集成电路芯片路由到刚性支撑基底上。 在支撑基体中形成孔，露出薄膜结构的下侧，从而允许将高密度连接器安装在薄膜结构的两个表面上，大大增强了在芯片模块中的相邻基板之间传递信号的能力。 这避免了将信号路由通过刚性支撑底座或薄膜结构的边缘的需要。 不需要高连接密度的电源和接地路径通过支持底座的低阻抗路径。 优选地，薄膜结构由诸如铜的图案化金属的交替层和诸如聚酰亚胺的低介电有机聚合物制成。

公开(公告)号：US06187652B1

公开(公告)日：2001-02-13

申请号：US09152365

申请日：1998-09-14

申请人： William T. Chou ,  Solomon I. Beilin ,  Michael Guang-Tzong Lee ,  Michael G. Peters ,  Wen-Chou Vincent Wang

发明人： William T. Chou ,  Solomon I. Beilin ,  Michael Guang-Tzong Lee ,  Michael G. Peters ,  Wen-Chou Vincent Wang

IPC分类号： H01L2130

CPC分类号： H05K3/4623

摘要： A method of fabricating a multi-layer interconnected substrate structure. The inventive method includes forming a multi-layer structure from multiple, pre-fabricated power and/or signal substrates which are laminated together. A drill is then used to form a via through the surface of a ring-type pad down to a desired depth in the multi-layer structure. The via hole is cleaned and then filled with a conductive material. The via so formed between two or more substrates is self-aligned by using the ring pad(s). This contributes to an increased signal routing density compared to conventional methods.

摘要翻译： 一种制造多层互连衬底结构的方法。 本发明的方法包括从层压在一起的多个预制电源和/或信号基板形成多层结构。 然后使用钻头在多层结构中通过环型垫的表面形成通孔，直到所需的深度。 通孔被清洁，然后用导电材料填充。 通过使用环形垫，在两个或更多个基板之间形成的通孔是自对准的。 与常规方法相比，这有助于提高信号路由密度。

公开(公告)号：US06706546B2

公开(公告)日：2004-03-16

申请号：US09757052

申请日：2001-01-08

申请人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Kiyoshi Kuwabara ,  Solomon I. Beilin ,  Michael Peters ,  Wen-Chou Vincent Wang ,  Masaaki Inao

发明人： Tetsuzo Yoshimura ,  Yashuhito Takahashi ,  Kiyoshi Kuwabara ,  Solomon I. Beilin ,  Michael Peters ,  Wen-Chou Vincent Wang ,  Masaaki Inao

IPC分类号： H01L2100

CPC分类号： G02B6/10 ,  G02B6/06 ,  G02B6/12002 ,  G02B6/124 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136 ,  G02B6/26 ,  G02B6/42 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12104 ,  G02B2006/12107 ,  G02B2006/12173 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/167 ,  H01L2221/68345 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0274 ,  H05K1/14 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05664

摘要： A method of constructing an electronic circuit assembly comprising forming at least one electrode on a substrate; forming a layer of undercladding material upon the substrate and over the electrode; and forming a wave guide core layer on the layer of cladding material. The wave guide layer is patterned to produce at least one optical wave guide and exposed undercladding material. The method of constructing further includes forming a layer of overcladding material upon the exposed undercladding material and over the optical wave guide; forming at least one via aperture through the overcladding material and the undercladding material; and disposing a conductive material in the via aperture to produce an electronic circuit assembly.

摘要翻译： 一种构造电子电路组件的方法，包括在衬底上形成至少一个电极; 在衬底上并在电极上形成下层材料层; 以及在包层材料层上形成波导芯层。 波导层被图案化以产生至少一个光波导和暴露的底层材料。 构造方法还包括在暴露的下包层材料上并在光波导上形成一层外包材料; 通过所述外包层材料和所述下包层材料形成至少一个通孔; 并将导电材料设置在通孔中以产生电子电路组件。

公开(公告)号：US07148569B1

公开(公告)日：2006-12-12

申请号：US10936196

申请日：2004-09-07

申请人： Wen-Chou Vincent Wang

发明人： Wen-Chou Vincent Wang

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/49816 ,  H01L23/498 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to a new bonding pad structure that includes a copper pad and a pad surface finish comprising multiple layers of solder. The multiple layers of solder include at least a layer of eutectic solder (or a layer of pure-Sn solder) covering the copper pad and a layer of high-Pb solder covering the layer of eutectic solder (or the layer of pure-Sn solder). Since the layer of high-Pb solder is significantly thicker than the eutectic solder layer (or the layer of pure-Sn solder), there is insufficient tin supply in the eutectic solder (or the layer of pure-Sn solder) for forming a thick Cu/Sn intermetallic layer on the copper pad. Instead, a thin Cu/Sn intermetallic layer is formed on the copper pad and there is less likelihood of forming a crack in the thin Cu/Sn intermetallic layer.

摘要翻译： 本发明涉及一种新的焊盘结构，其包括铜焊盘和包括多层焊料的焊盘表面光洁度。 多层焊料包括覆盖铜焊盘的至少一层共晶焊料（或纯Sn焊料层）和覆盖共晶焊料层（或纯Sn焊料层）的高Pb焊料层 ）。 由于高Pb焊料层比共晶焊料层（或纯Sn焊料层）显着更厚，所以在共晶焊料（或纯Sn焊料层）中锡供应不足，用于形成厚的 Cu / Sn金属层在铜垫上。 相反，在铜焊盘上形成薄的Cu / Sn金属间层，并且在薄的Cu / Sn金属间层中形成裂纹的可能性较小。

公开(公告)号：US06882045B2

公开(公告)日：2005-04-19

申请号：US09997589

申请日：2001-11-29

申请人： Thomas J. Massingill ,  Mark Thomas McCormack ,  Wen-Chou Vincent Wang

发明人： Thomas J. Massingill ,  Mark Thomas McCormack ,  Wen-Chou Vincent Wang

IPC分类号： H01L21/48 ,  H05K3/00 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46 ,  H01L23/34

CPC分类号： H01L21/486 ,  H01L24/96 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/16501 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4602 ,  H05K3/4647 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1383 ,  H01L2924/01049 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

摘要翻译： 一种用于去除有缺陷的电容器的方法，包括在半导体衬底上形成多个电容器，在多个电容器上形成多个金属触点，并在半导体衬底上沉积一层光致抗蚀剂。 图案化光致抗蚀剂层，使得多个金属触点暴露，然后与导电溶液接触。 随后将金属触点设置在不良电容器上，随后被去掉。 一种用于形成多芯片模块的方法，包括形成具有一对侧面的薄膜聚合物互连结构，其中一个侧面设置在具有有源或无源器件的硅衬底上，并且另一个具有安装在其上的计算机芯片。 通过该方法形成的多芯片模块。

公开(公告)号：US07144756B1

公开(公告)日：2006-12-05

申请号：US11126571

申请日：2005-05-10

申请人： Wen-Chou Vincent Wang ,  Donald S. Fritz ,  Yuan Li

发明人： Wen-Chou Vincent Wang ,  Donald S. Fritz ,  Yuan Li

IPC分类号： H01I21/44

CPC分类号： H01L23/36 ,  H01L21/563 ,  H01L23/055 ,  H01L23/5329 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

摘要翻译： 提供了一种用于这种封装的翘曲控制和制造方法的半导体低K Si晶片倒装芯片封装。 这些包装包括附着在低K Si管芯和封装基板上的散热器。 通常，用于将散热器连接到低K Si管芯的热界面材料的模量相对于其它市售的热界面材料选择得尽可能高。 另一方面，用于通过可选的加强筋将散热器连接到基底上的粘合剂的模量相对于其它市售粘合剂选择尽可能低。 结果是具有较低弯曲度和如此改进的共面性（符合行业规范）与其最终结合的表面的封装。 此外，由此提高了低K Si管芯和封装可靠性。

公开(公告)号：US06909176B1

公开(公告)日：2005-06-21

申请号：US10719451

申请日：2003-11-20

申请人： Wen-Chou Vincent Wang ,  Donald S. Fritz ,  Yuan Li

发明人： Wen-Chou Vincent Wang ,  Donald S. Fritz ,  Yuan Li

IPC分类号： H01L21/56 ,  H01L23/055 ,  H01L23/36 ,  H01L23/532 ,  H01L23/10

CPC分类号： H01L23/36 ,  H01L21/563 ,  H01L23/055 ,  H01L23/5329 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： Provided are a semiconductor low-K Si die flip chip package with warpage control and fabrication methods for such packages. The packages include heat spreaders that are attached to the low-K Si die and packaging substrate. In general, the modulus of the thermal interface material, which is used to attach the heat spreader to the low-K Si die, is selected as high as possible relative to other commercially available thermal interface materials. On the other hand, the modulus of the adhesive, which is used to attach the heat spreader via an optional stiffener to the substrate, is selected as low as possible relative to other commercially available adhesives. The result is a package with less bowing and so improved co-planarity (in compliance with industry specifications) with the surface to which it is ultimately bound. Moreover, the low-K Si die and package reliabilities are thereby enhanced.

摘要翻译： 提供了一种用于这种封装的翘曲控制和制造方法的半导体低K Si晶片倒装芯片封装。 这些包装包括附着在低K Si管芯和封装基板上的散热器。 通常，用于将散热器连接到低K Si管芯的热界面材料的模量相对于其它市售的热界面材料选择得尽可能高。 另一方面，用于通过可选的加强筋将散热器连接到基底上的粘合剂的模量相对于其它市售粘合剂选择尽可能低。 结果是具有较低弯曲度和如此改进的共面性（符合行业规范）与其最终结合的表面的封装。 此外，由此提高了低K Si管芯和封装可靠性。

公开(公告)号：US5655290A

公开(公告)日：1997-08-12

申请号：US380083

申请日：1995-01-30

申请人： Larry L. Moresco ,  David A. Horine ,  Wen-Chou Vincent Wang

发明人： Larry L. Moresco ,  David A. Horine ,  Wen-Chou Vincent Wang

IPC分类号： H01L21/48 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H05K1/14 ,  H05K3/36

CPC分类号： H01L23/4985 ,  H01L21/486 ,  H01L23/473 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0652 ,  H05K1/144 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/3011 ,  Y10T29/49126

摘要： A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained. The overall design of the three dimensional structure of the present invention is highly modular to facilitate high yield fabrication and repair.

摘要翻译： 示出了用于容纳多个集成电路芯片的三维模块。 IC芯片以多个基板的方式安装。 平行于每行是提供信号路径的通信条，允许一个基板上的芯片与另一个基板上的芯片通信。 通信条也用作衬底之间的间隔物，从而形成冷却通道。 IC芯片设置在冷却通道中，使得它们与冷却流体直接接触。 来往于IC芯片的信号线保持尽可能与电源线分开，以使噪声最小化。 为此，相对较厚的电源带安装到每行IC芯片下方的每个基板。 电源带又连接到馈电带，使得保持到IC芯片的非常低的阻抗电源路径。 本发明的三维结构的总体设计是高度模块化的，以便于高产量的制造和修理。