公开(公告)号：US20060252199A1

公开(公告)日：2006-11-09

申请号：US11458224

申请日：2006-07-18

Applicant: Min Yoo

Inventor： Min Yoo

IPC: H01L21/8242

CPC classification number: H01L29/0653 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having the SiGe film formed thereon, selectively etching the SiGe film, embedding a dielectric material into a portion where the SiGe film is removed, forming a stepped profile on the silicon film by etching a predetermined portion of the silicon film such that the bit-line node portion is included in the stepped profile, and forming a gate on the silicon film having the stepped profile formed therein such that the gate overlaps the stepped profile. The dielectric pad prevents the bit-line junction from spreading downward upon operation of the gate, thereby enhancing a punch-through phenomenon.

Abstract translation: 这里公开了一种在半导体器件中形成栅极结构的方法。 该方法包括在对应于形成位线结的位线节点部分的硅衬底的预定区域上形成SiGe膜，在其上形成有SiGe膜的硅衬底上生长硅膜，选择性地蚀刻 SiGe膜，将介电材料嵌入到去除SiGe膜的部分中，通过蚀刻硅膜的预定部分使得在硅膜上形成阶梯形轮廓，使得位线节点部分包括在阶梯轮廓中，以及 在硅膜上形成具有形成在其中的阶梯轮廓的栅极，使得栅极与阶梯轮廓重叠。 电介质垫在栅极操作时防止位线结面向下扩展，从而增强穿通现象。

公开(公告)号：US07843052B1

公开(公告)日：2010-11-30

申请号：US12270690

申请日：2008-11-13

Applicant: Min Yoo ,  Ki Wook Lee ,  Min Jae Lee

Inventor： Min Yoo ,  Ki Wook Lee ,  Min Jae Lee

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

Abstract: Semiconductor devices are disclosed. In an embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die. The stack of the second semiconductor dies is encapsulated by an encapsulant. Redistribution layers are formed on one surface of the stack and are connected to the through-silicon vias. Solder balls are attached to the respective redistribution layers. In another embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die formed with through-silicon vias. Redistribution layers are formed on the back surface of the first semiconductor die. Solder balls are attached to the respective redistribution layers. Further disclosed are methods for fabricating the semiconductor devices.

Abstract translation: 公开了半导体器件。 在一个实施例中，形成有穿硅通孔的多个第二半导体管芯被堆叠在第一半导体管芯上。 第二半导体管芯的堆叠由密封剂封装。 再分布层形成在堆叠的一个表面上并且连接到穿硅通孔。 焊球附着在相应的再分布层上。 在另一个实施例中，形成有穿硅通孔的多个第二半导体管芯被堆叠在形成有通孔硅通孔的第一半导体管芯上。 在第一半导体管芯的后表面上形成再分布层。 焊球附着在相应的再分布层上。 还公开了制造半导体器件的方法。

公开(公告)号：US07718523B1

公开(公告)日：2010-05-18

申请号：US11875597

申请日：2007-10-19

Applicant: Min Yoo ,  Tae Seong Kim ,  Ji Young Chung

Inventor： Min Yoo ,  Tae Seong Kim ,  Ji Young Chung

IPC: H01L21/44

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/03828 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/111 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K2201/10734 ,  H05K2203/033 ,  H05K2203/043 ,  H05K2203/0485 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Abstract translation: 焊接附着膜包括第一覆盖膜，焊剂层，焊料层和第二覆盖膜，并且其可以被处理或保持为辊状。 使用焊料附着膜的焊球形成方法包括制备半导体封装或半导体管芯，粘附焊料附着膜，网格化和回流。 在焊料附着膜附着操作中，去除第一覆盖膜和第二覆盖膜，并且将焊剂层粘附到半导体封装或半导体管芯的导电焊盘。 随后，在回流操作中，磁通层被挥发除去，焊料层被熔融固定在导电焊盘上，从而形成焊球。

公开(公告)号：US08294276B1

公开(公告)日：2012-10-23

申请号：US12788845

申请日：2010-05-27

Applicant: Sang Won Kim ,  Boo Yang Jung ,  Sung Kyu Kim ,  Min Yoo ,  Seung Jae Lee

Inventor： Sang Won Kim ,  Boo Yang Jung ,  Sung Kyu Kim ,  Min Yoo ,  Seung Jae Lee

IPC: H01L23/12

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device and a fabricating method thereof are provided. In one exemplary embodiment, a plurality of semiconductor dies are mounted on a laminating member, for example, a copper clad lamination, having previously formed conductive patterns, followed by performing operations of encapsulating, forming conductive vias, forming a solder resist and sawing, thereby fabricating a chip size package in a simplified manner. Fiducial patterns are further formed on the laminating member, thereby accurately positioning the semiconductor dies at preset positions of the laminating member.

Abstract translation: 提供了一种半导体器件及其制造方法。 在一个示例性实施例中，多个半导体管芯安装在具有预先形成的导电图案的层压构件，例如铜包覆层压件上，然后执行封装，形成导电通孔，形成阻焊剂和锯切的操作，由此 以简化的方式制造芯片尺寸封装。 在层叠构件上还形成有基准图案，从而将半导体模具精确地定位在层叠构件的预定位置。

公开(公告)号：US08004078B1

公开(公告)日：2011-08-23

申请号：US12405854

申请日：2009-03-17

Applicant: Jae Kyu Song ,  Bong Chan Kim ,  Min Yoo

Inventor： Jae Kyu Song ,  Bong Chan Kim ,  Min Yoo

IPC: H01L23/48 ,  G02B6/12

CPC classification number: H01L24/29 ,  C08K3/14 ,  C08K3/38 ,  C09J7/38 ,  C09J2205/102 ,  C09J2467/00 ,  C09J2475/00 ,  H01L23/293 ,  H01L23/295 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29393 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided is an adhesive composition for a semiconductor device. For example, the adhesive composition comprises a binder resin and a silicon carbide filler. The silicon carbide filler has relatively high thermal conductivity and a relatively low coefficient of thermal expansion (CTE). Accordingly, the adhesive composition containing the silicon carbide filler exhibits improved heat dissipation performance and electrical performance due to high thermal conductivity and shows inhibition of delamination or cracking of semiconductor devices due to low CTE. The silicon carbide has high thermal conductivity, but is electrically non-conductive. Therefore, an electrically conductive adhesive can be obtained by additional incorporation of a silver (Ag) filler into the binder resin.

Abstract translation: 本发明提供一种半导体装置用粘合剂组合物。 例如，粘合剂组合物包含粘合剂树脂和碳化硅填料。 碳化硅填料具有较高的热导率和较低的热膨胀系数（CTE）。 因此，含有碳化硅填料的粘合剂组合物由于高导热性而具有改善的散热性能和电性能，并且由于低CTE而显示出对半导体器件的分层或破裂的抑制。 碳化硅具有高导热性，但是是非导电的。 因此，通过向粘合剂树脂中另外并入银（Ag）填料可以获得导电粘合剂。

公开(公告)号：US20060145200A1

公开(公告)日：2006-07-06

申请号：US11174788

申请日：2005-07-05

Applicant: Min Yoo

Inventor： Min Yoo

IPC: H01L31/112

CPC classification number: H01L29/0653 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

Abstract: Disclosed herein is a method for forming a gate structure in a semiconductor device. The method comprises forming a SiGe film on a predetermined region of a silicon substrate corresponding to a bit-line node portion where a bit-line junction is formed, growing a silicon film over the silicon substrate having the SiGe film formed thereon, selectively etching the SiGe film, embedding a dielectric material into a portion where the SiGe film is removed, forming a stepped profile on the silicon film by etching a predetermined portion of the silicon film such that the bit-line node portion is included in the stepped profile, and forming a gate on the silicon film having the stepped profile formed therein such that the gate overlaps the stepped profile. The dielectric pad prevents the bit-line junction from spreading downward upon operation of the gate, thereby enhancing a punch-through phenomenon.

Abstract translation: 这里公开了一种在半导体器件中形成栅极结构的方法。 该方法包括在对应于形成位线结的位线节点部分的硅衬底的预定区域上形成SiGe膜，在其上形成有SiGe膜的硅衬底上生长硅膜，选择性地蚀刻 SiGe膜，将介电材料嵌入到去除SiGe膜的部分中，通过蚀刻硅膜的预定部分使得在硅膜上形成阶梯形轮廓，使得位线节点部分包括在阶梯轮廓中，以及 在硅膜上形成具有形成在其中的阶梯轮廓的栅极，使得栅极与阶梯轮廓重叠。 电介质垫在栅极操作时防止位线结面向下扩展，从而增强穿通现象。

公开(公告)号：US08441123B1

公开(公告)日：2013-05-14

申请号：US12540593

申请日：2009-08-13

Applicant: Dong Hee Lee ,  Min Yoo ,  Dae Byoung Kang ,  Bae Yong Kim

Inventor： Dong Hee Lee ,  Min Yoo ,  Dae Byoung Kang ,  Bae Yong Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/014

Abstract: A semiconductor device has a first semiconductor die having at least one metal pillar formed along an inner perimeter and at least one bond pad formed along an outer perimeter. A second semiconductor die has at least one metal pillar. A conductive bump connects the at least one metal pillar of the first semiconductor die to the at least one metal pillar of the second semiconductor die. At least one metal dam is formed on the first semiconductor die between the at least one metal pillar of the first semiconductor die and the at least one bond pad.

Abstract translation: 半导体器件具有第一半导体管芯，该第一半导体管芯具有沿着内周边形成的至少一个金属柱和沿外周形成的至少一个接合焊盘。 第二半导体管芯具有至少一个金属柱。 导电凸块将第一半导体管芯的至少一个金属柱连接到第二半导体管芯的至少一个金属柱。 在第一半导体管芯上的至少一个金属柱与第一半导体管芯的至少一个接合焊盘之间形成至少一个金属坝。

公开(公告)号：US08089148B1

公开(公告)日：2012-01-03

申请号：US12539116

申请日：2009-08-11

Applicant: Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

Inventor： Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

Abstract translation: 电路板具有包括与第一表面相对的第一表面和第二表面的绝缘层。 在绝缘层的第一表面上形成多个导电图案。 导电焊盘形成在绝缘层的第一表面的管芯安装区域中，并且与第一表面上的多个导电图案之一电连接。 延伸图案从导电焊盘延伸到安装区域的外部。 保护层覆盖绝缘层的第一表面和导电图案。 在保护层中形成沟槽以暴露导电焊盘和延伸图案。

公开(公告)号：US07859107B1

公开(公告)日：2010-12-28

申请号：US12798412

申请日：2010-04-02

Applicant: Min Yoo ,  Tae Seong Kim ,  Ji Young Chung

Inventor： Min Yoo ,  Tae Seong Kim ,  Ji Young Chung

IPC: H01L23/12

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/03828 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/111 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H05K2201/10734 ,  H05K2203/033 ,  H05K2203/043 ,  H05K2203/0485 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A solder attach film includes a first cover film, a flux layer, a solder layer, and a second cover film, and it can be treated or kept in a roll shape. A solder ball forming method using the solder attach film includes preparing a semiconductor package or a semiconductor die, adhering the solder attach film, gridding, and reflowing. In the solder attach film adhering operation, the first cover film and the second cover film are removed, and the flux layer is adhered to electrically conductive pads of the semiconductor package or the semiconductor die. Subsequently, in the reflowing operation, the flux layer is volatilized and removed, and the solder layer is fused and fixed to the electrically conductive pads, so that solder balls are formed.

Abstract translation: 焊接附着膜包括第一覆盖膜，焊剂层，焊料层和第二覆盖膜，并且其可以被处理或保持为辊状。 使用焊料附着膜的焊球形成方法包括制备半导体封装或半导体管芯，粘附焊料附着膜，网格化和回流。 在焊料附着膜附着操作中，去除第一覆盖膜和第二覆盖膜，并且将焊剂层粘附到半导体封装或半导体管芯的导电焊盘。 随后，在回流操作中，磁通层被挥发除去，焊料层被熔融固定在导电焊盘上，从而形成焊球。