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    Method of manufacturing semiconductor device
    1.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07468297B2

    公开(公告)日：2008-12-23

    申请号：US11099699

    申请日：2005-04-06

    申请人： Toshiro Futatsugi ,  Naoto Horiguchi ,  Ken-ichi Okabe ,  Kenichi Hikazutani

    发明人： Toshiro Futatsugi ,  Naoto Horiguchi ,  Ken-ichi Okabe ,  Kenichi Hikazutani

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/40 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L27/0629 ,  H01L29/94

    摘要： A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.

    摘要翻译： 一种制造半导体器件的方法，包括：通过以第一剂量注入杂质，在半导体衬底的第一区域中形成第一杂质扩散区域作为电容器的下电极; 通过以第二剂量注入杂质，在半导体衬底的端部的第二区域中形成第二杂质扩散区; 并通过热氧化法形成在第一杂质扩散区上具有第一厚度的电容器绝缘膜，并形成第二厚度比第二区域厚的第二厚度的氧化膜。

    Non-volatile semiconductor memory device having gate insulating film with thick end sections
    2.
    发明授权
    Non-volatile semiconductor memory device having gate insulating film with thick end sections 有权
    具有栅极绝缘膜的非易失性半导体存储器件具有较厚的端部

    公开(公告)号：US06774430B2

    公开(公告)日：2004-08-10

    申请号：US09984215

    申请日：2001-10-29

    申请人： Naoto Horiguchi ,  Toshiro Futatsugi

    发明人： Naoto Horiguchi ,  Toshiro Futatsugi

    IPC分类号： H01L29788

    CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    摘要： A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.

    摘要翻译： 一种非易失性半导体存储器，包括半导体衬底，形成在衬底上的栅极绝缘膜，并且具有薄的中心部分和厚的端部部分，形成在速率绝缘膜上的浮动栅极，形成在所述衬底上的电极间绝缘膜 浮置栅极，形成在电极间绝缘膜上的控制栅极以及形成在浮动栅极两侧的基板中的源极/漏极区域，并且具有在浮动栅极的厚端部下方延伸的延伸部，并且与薄膜 栅极绝缘膜的中心部分，其中薄的中心部分能够使载体在低施加电压下隧道化，并且厚端部部分防止存储的电荷隧道到延伸部并且增强存储的电荷的保留。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5031005A

    公开(公告)日：1991-07-09

    申请号：US111018

    申请日：1987-10-21

    申请人： Toshiro Futatsugi ,  Naoki Yokoyama ,  Kenichi Imamura

    发明人： Toshiro Futatsugi ,  Naoki Yokoyama ,  Kenichi Imamura

    IPC分类号： H01L29/08 ,  H01L29/205 ,  H01L29/737 ,  H01L33/00

    CPC分类号： H01L29/7376 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/205 ,  H01L33/0004

    摘要： A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.

    摘要翻译： 半导体器件包括堆叠的第一至第五半导体层。 半导体器件具有| Ec3-Ec1 | APPROX | Ev3-Ev5|的能级条件，其中Ec3是第三层导带中的电子的共振能级，Ev3是化合价中的空穴的共振能级 并且Ec1是第一层的导带的能级，Ev5是第五层的价带的能级。

    Semiconductor memory with floating gate type FET
    9.
    发明授权
    Semiconductor memory with floating gate type FET 有权
    具有浮栅型FET的半导体存储器

    公开(公告)号：US06195292B1

    公开(公告)日：2001-02-27

    申请号：US09437142

    申请日：1999-11-10

    申请人： Tatsuya Usuki ,  Toshiro Futatsugi

    发明人： Tatsuya Usuki ,  Toshiro Futatsugi

    IPC分类号： G11C1604

    CPC分类号： H01L29/7883 ,  G11C16/0416 ,  H01L29/42324 ,  H01L29/4966

    摘要： A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction. Materials of the floating gate electrode and channel region are selected so that a Fermi level of the floating gate electrode is positioned in an energy band gap of the channel region when an external voltage is not applied between the channel region and the control gate electrode.

    摘要翻译： 源极区域和漏极区域形成在表面层中限定的沟道区域的两侧的半导体衬底的表面层中。 隧道绝缘膜形成在沟道区上，隧道绝缘膜具有允许载流子穿过其的厚度。 在隧道绝缘膜上形成浮栅电极，浮置栅电极沿着衬底法线方向设置成不与源极区域和漏极区域重叠。 栅极绝缘膜形成在通道区域上，覆盖浮栅电极。 控制栅电极形成在栅极绝缘膜上，控制栅电极设置成沿着衬底法线方向与源区和漏区接触或部分重叠。 选择浮栅电极和沟道区的材料，使得当沟道区和控制栅电极之间没有施加外部电压时，浮置栅电极的费米能级位于沟道区的能带隙中。