公开(公告)号：US20120279287A1

公开(公告)日：2012-11-08

申请号：US13101253

申请日：2011-05-05

申请人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

发明人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

IPC分类号： G01B5/28 ,  B05D5/00 ,  C23F1/00

CPC分类号： G01B5/28 ,  B81B2201/12 ,  B81C3/001 ,  B81C2201/0194 ,  G01Q40/02 ,  G01Q70/14 ,  G01Q70/16 ,  G01R1/067 ,  G01R1/06738 ,  G01R1/07378 ,  G01R3/00 ,  G03F7/00

摘要： Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.

摘要翻译： 本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在探针的未被分层的覆盖部分处接触金属探针。 此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构， 以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。 此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

公开(公告)号：US09200883B2

公开(公告)日：2015-12-01

申请号：US13101253

申请日：2011-05-05

申请人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

发明人： Paul S. Andry ,  Bing Dang ,  Steven L. Wright

IPC分类号： G01N27/84 ,  G01R33/12 ,  G01R31/26 ,  H01L21/66 ,  H01L21/44 ,  G01B5/28 ,  G03F7/00 ,  G01R1/073 ,  G01R3/00 ,  G01Q70/14 ,  G01R1/067 ,  G01Q70/16 ,  G01Q40/02

CPC分类号： G01B5/28 ,  B81B2201/12 ,  B81C3/001 ,  B81C2201/0194 ,  G01Q40/02 ,  G01Q70/14 ,  G01Q70/16 ,  G01R1/067 ,  G01R1/06738 ,  G01R1/07378 ,  G01R3/00 ,  G03F7/00

摘要： Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.

摘要翻译： 本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在未被分层的被覆层的探针的一部分处接触金属探针。 此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构， 以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。 此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

公开(公告)号：US08559474B2

公开(公告)日：2013-10-15

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01S5/024 ,  H01S5/18 ,  H01L23/28 ,  H01L23/18

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US08290008B2

公开(公告)日：2012-10-16

申请号：US12544696

申请日：2009-08-20

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC分类号： H01S5/022 ,  H01S5/024

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US20120326290A1

公开(公告)日：2012-12-27

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US20090311849A1

公开(公告)日：2009-12-17

申请号：US12140492

申请日：2008-06-17

申请人： Paul S. Andry ,  Bing Dang ,  Matthew J. Farinelli ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Bing Dang ,  Matthew J. Farinelli ,  Cornelia K. Tsang

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68381 ,  H01L2224/16 ,  H01L2924/14

摘要： Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips.

摘要翻译： 提供了分离在单个晶片上制造的集成电路芯片的改进的方法。 在一个实施例中，分离在晶片上制造的集成电路芯片的方法包括：将支撑件附接到晶片的背面; 切割晶片以形成附接到支撑件的单个集成电路芯片; 将包含可释放粘合剂材料的载体附接到所述晶片的与所述后表面相对的前表面; 将支撑体从晶片的背面分离; 使载体经受有效量的热量，辐射或两者以降低粘合剂材料的粘附性，以允许将集成电路芯片中的至少一个从载体上移除; 以及使用构造成处理集成电路芯片的工具来拾取和移动至少一个集成电路芯片。

公开(公告)号：US08388782B2

公开(公告)日：2013-03-05

申请号：US12788832

申请日：2010-05-27

申请人： Paul S. Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prahbakar ,  Peter J. Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

发明人： Paul S. Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prahbakar ,  Peter J. Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC分类号： B32B38/10 ,  B32B37/12

CPC分类号： H01L21/67132 ,  C09J5/06 ,  C09J2203/326 ,  C09J2479/08 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68381 ,  Y10T156/1158

摘要： A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.

摘要翻译： 一种用于将处理器附接到晶片的方法，所述晶片包括集成电路（IC），包括在所述晶片上形成粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。 一种用于将处理器附接到晶片的系统，包括IC的晶片包括位于晶片上的粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。

公开(公告)号：US20110044369A1

公开(公告)日：2011-02-24

申请号：US12544696

申请日：2009-08-20

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC分类号： H01S5/18 ,  H01L31/0232 ,  H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US20090178275A1

公开(公告)日：2009-07-16

申请号：US12348115

申请日：2009-01-02

申请人： Bing Dang ,  Steven L. Wright

发明人： Bing Dang ,  Steven L. Wright

IPC分类号： H05K3/00

CPC分类号： H01L23/345 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  Y10T29/4913 ,  H01L2924/00

摘要： Forming a silicon carrier interposer having an integrated heater includes forming a multi-layer silicon member having a main body portion including a first surface, a second surface and an intermediate portion, and attaching first and second electronic components to the first surface of the multi-layer silicon member. A plurality of vias extend between the first surface and the second surface and are adapted to provide an interface between the first and second electronic components and a substrate. In addition, a plurality of heating elements are integrated into the main body portion of the multi-layer silicon member. The heating elements are selectively activated to create a reflow of solder to facilitate one of an attachment of one of the first and second electronic components to the multi-layer silicon member and a detachment of the one of the first and second electronic components from the multi-layer silicon member.

摘要翻译： 形成具有集成加热器的硅载体插入件包括形成具有包括第一表面，第二表面和中间部分的主体部分的多层硅元件，以及将第一和第二电子元件附接到多层硅片的第一表面， 层硅构件。 多个通孔在第一表面和第二表面之间延伸并且适于提供第一和第二电子部件与基板之间的界面。 另外，多层加热元件集成在多层硅构件的主体部分中。 加热元件被选择性地激活以产生焊料的回流，以促进第一和第二电子元件中的一个附着到多层硅元件中的一个以及第一和第二电子元件中的一个与多层硅元件的分离 层硅构件。

公开(公告)号：US07474540B1

公开(公告)日：2009-01-06

申请号：US11972388

申请日：2008-01-10

申请人： Bing Dang ,  Steven L. Wright

发明人： Bing Dang ,  Steven L. Wright

IPC分类号： H05K1/11

CPC分类号： H01L23/345 ,  H01L23/147 ,  H01L23/5384 ,  H01L24/81 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/81234 ,  H01L2224/81815 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  Y10T29/4913 ,  H01L2924/00

摘要： A silicon carrier package includes a multi-layer member having at least a first layer and a second layer. A first electronic component includes a plurality of connector members that establish a first bond electrically interconnecting the first electronic component to the multi-layer member. A second electronic component includes a plurality of connector members that establish a second bond electrically interconnecting the second electronic component to the multi-layer member. At least one heating element is integrated into one of the first and second layers of the multi-layer member. The at least one heating element is selectively activated to loosen only one of the first and second bonds to facilitate removal of only one of the first and second electronic components from the multi-layer member. The other of the first and second bonds remains intact.

摘要翻译： 硅载体封装包括具有至少第一层和第二层的多层构件。 第一电子部件包括多个连接器构件，其建立将第一电子部件电连接到多层部件的第一接合部。 第二电子部件包括多个连接器构件，其建立将第二电子部件电连接到多层部件的第二接合部。 至少一个加热元件集成到多层构件的第一层和第二层之一中。 选择性地激活至少一个加热元件以松开仅第一和第二键中的一个，以便于从多层构件中仅去除第一和第二电子部件中的仅一个。 第一和第二债券中的另一个保持不变。