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    Methods and apparatus for testing integrated circuits
    1.
    发明授权
    Methods and apparatus for testing integrated circuits 有权
    集成电路测试方法和设备

    公开(公告)号：US06560735B1

    公开(公告)日：2003-05-06

    申请号：US09366388

    申请日：1999-08-03

    申请人： Louis Nelson Ahlquist ,  Yinon Degani ,  Jericho J. Jacala ,  Dean Paul Kossives ,  King Lien Tai

    发明人： Louis Nelson Ahlquist ,  Yinon Degani ,  Jericho J. Jacala ,  Dean Paul Kossives ,  King Lien Tai

    IPC分类号： G01R3128

    CPC分类号： G01R31/2853

    摘要： The specification describes an IC test apparatus having a test bed with sockets adapted to engage arrays of I/O solder balls/bumps on the IC chip. In one embodiment the sockets are provided with through holes to interconnect the solder bumps to the next board level with minimum electrical path length thereby reducing parasitic capacitive coupling. In another embodiment the sockets in the test bed are formed by intersecting V-grooves. If pairs of intersecting V-grooves are used, pyramid shaped features are produced at the bottom of each socket. Both the sharp edges formed by the intersecting V-grooves and the pyramid provide contact enhancement between the solder bumps and the test bed. The test bed can be made as a universal blank for a given solder bump pitch. The desired test circuit is formed at the next board level.

    摘要翻译： 本说明书描述了一种具有测试台的IC测试装置，其具有适于接合IC芯片上的I / O焊球/凸起阵列的插座。 在一个实施例中，插座设置有通孔，以将焊料凸块互连到具有最小电路长度的下一个电路板级，从而减少寄生电容耦合。 在另一个实施例中，试验台中的插座由V形槽相交形成。 如果使用成对的相交的V形槽，则在每个插座的底部产生金字塔形特征。 由相交的V形槽和金字塔形成的锐利边缘都提供焊料凸块和试验台之间的接触增强。 测试台可以作为给定焊料凸块间距的通用坯料。 所需的测试电路在下一个电路板级形成。

    Manufacture of printed circuit cards
    2.
    发明授权
    Manufacture of printed circuit cards 失效
    印刷电路卡的制造

    公开(公告)号：US06370766B1

    公开(公告)日：2002-04-16

    申请号：US08807266

    申请日：1997-02-28

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  Dean Paul Kossives ,  Yee Leng Low

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  Dean Paul Kossives ,  Yee Leng Low

    IPC分类号： H05K330

    CPC分类号： H05K1/0268 ,  G01R31/2818 ,  H05K3/0052 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： The specification describes methods for the manufacture of printed circuit cards which allow for final testing, including burn-in if required, of multiples of printed circuit cards as an integrated process panel prior to final packaging and singulation. This desired sequence of operations is made possible by the addition of arrays of test contacts at the edge of the integrated process panel where the test contacts can be accessed with an insertion test apparatus.

    摘要翻译： 本说明书描述了用于制造印刷电路卡的方法，其允许最终测试，包括如果需要，在最终包装和分割之前作为集成处理面板的多个印刷电路卡进行最终测试。 通过在集成处理面板的边缘添加测试触点的阵列，可以使用插入测试装置访问测试触点，从而可以实现所需的操作顺序。

    Cleaning solder-bonded flip-chip assemblies
    4.
    发明授权
    Cleaning solder-bonded flip-chip assemblies 失效
    清洁焊接的倒装芯片组件

    公开(公告)号：US5778913A

    公开(公告)日：1998-07-14

    申请号：US803474

    申请日：1997-02-20

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  Dean Paul Kossives

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  Dean Paul Kossives

    IPC分类号： B08B3/04 ,  H01L21/00 ,  B08B3/02

    CPC分类号： H01L21/67051 ,  B08B3/04 ,  Y10S134/902

    摘要： Cleaning of a micromimiature high-density flip-chip assembly is carried out by spinning the assembly while applying cleaning fluid to a central portion of the assembly. Confinement of the cleaning fluid to a critical interconnection space of the assembly is ensured by a centrally apertured cover that resiliently engages the top of the assembly. During spinning, cleaning fluid is introduced through the aperture in the cover and is directed into and confined to flow radially in the interconnection space.

    摘要翻译： 通过在将组件的中央部分应用清洁流体的同时旋转组件来进行微型高密度倒装芯片组件的清洁。 通过与组件的顶部弹性接合的中心有孔盖确保清洁流体到组件的关键互连空间的限制。 在纺纱期间，清洁液通过盖中的孔引入并被引导并限制在互连空间中径向流动。

    Integrated passive devices
    6.
    发明申请
    Integrated passive devices 审中-公开
    集成无源器件

    公开(公告)号：US20090218655A1

    公开(公告)日：2009-09-03

    申请号：US12387706

    申请日：2009-05-06

    申请人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

    发明人： Yinon Degani ,  Maureen Y. Lau ,  King Lien Tai

    IPC分类号： H01L27/06 ,  B32B9/04

    CPC分类号： H01L28/40 ,  H01L27/016 ,  H01L27/101 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

    摘要翻译： 本说明书描述了形成在多晶硅衬底上的集成无源器件（IPD）。 公开了一种用于制造IPD的方法，其中从单晶晶片处开始制造多晶硅衬底，在起始晶片的一侧或两侧沉积厚的多晶硅衬底层，在多晶硅衬底层之一上形成IPD， 并移除手柄晶片。 在优选实施例中，单晶硅处理晶片是从单晶硅晶片生产线排除的硅晶片。

    Testing integrated circuits
    7.
    发明授权
    Testing integrated circuits 失效
    测试集成电路

    公开(公告)号：US07061258B2

    公开(公告)日：2006-06-13

    申请号：US10997629

    申请日：2004-11-24

    申请人： Yinon Degani ,  Charley Chunlei Gao ,  King Lien Tai

    发明人： Yinon Degani ,  Charley Chunlei Gao ,  King Lien Tai

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0735

    摘要： A flexible membrane test apparatus and test method for high-speed IC chips. The method and apparatus rely on locating the reference components of the test circuit very close to the contact pads of the IC chip under test. This is achieved in one embodiment by locating those components adjacent to the flexible membrane. In another embodiment, the reference components may be attached to the membrane itself, so the length of the runners connecting the contact points of the tester and the critical reference components is optimally reduced. In yet a further embodiment, the entire test circuit, in the form of an IC test chip, is located on the membrane.

    摘要翻译： 一种用于高速IC芯片的柔性膜测试装置和测试方法。 该方法和装置依赖于将测试电路的参考部件定位得非常靠近被测IC芯片的接触焊盘。 这在一个实施例中通过将这些部件定位在与柔性膜相邻的位置来实现。 在另一个实施例中，参考部件可以附接到膜本身，因此连接测试器的接触点和关键参考部件的流道的长度被最佳地减小。 在又一个实施例中，以IC测试芯片的形式的整个测试电路位于膜上。

    Packaging silicon on silicon multichip modules
    10.
    发明授权
    Packaging silicon on silicon multichip modules 失效
    包装硅多芯片模块

    公开(公告)号：US06369444B1

    公开(公告)日：2002-04-09

    申请号：US09081448

    申请日：1998-05-19

    申请人： Yinon Degani ,  Thomas Dixon Dudderar ,  King Lien Tai

    发明人： Yinon Degani ,  Thomas Dixon Dudderar ,  King Lien Tai

    IPC分类号： H01L2334

    CPC分类号： H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15151 ,  H01L2924/15321

    摘要： The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.

    摘要翻译： 该规范描述了硅上硅多芯片模块的互连组件。 硅上硅MCM安装在具有基本上与硅的CTE匹配的热膨胀系数（CTE）的环氧树脂/玻璃层压板上。 在优选实施例中，组件是具有卡边缘连接器的PC卡，即没有固定的焊料层间互连，使得可以修改包含卡的环氧树脂层压体的CTE，而不考虑与母板的潜在不匹配。