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39 条记录 (耗时 0.031 秒)

    Conducting paste for device level interconnects
    7.
    发明授权
    Conducting paste for device level interconnects 有权
    用于器件级互连的导电膏

    公开(公告)号：US08685284B2

    公开(公告)日：2014-04-01

    申请号：US12884657

    申请日：2010-09-17

    申请人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    IPC分类号： H01B1/00 ,  H01B1/22 ,  H01B1/02

    CPC分类号： H01B1/22 ,  H01L2224/81 ,  Y10T29/49117

    摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

    摘要翻译： 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。 通常，小于5微米的平均片尺寸适用于五微米互连。 然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量％。 纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

    CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS
    8.
    发明申请
    CONDUCTING PASTE FOR DEVICE LEVEL INTERCONNECTS 有权
    用于设备级互连的导电胶

    公开(公告)号：US20120069531A1

    公开(公告)日：2012-03-22

    申请号：US12884657

    申请日：2010-09-17

    申请人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    发明人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

    IPC分类号： H05K7/00 ,  H01B1/02 ,  H01B1/22 ,  H01R43/00

    CPC分类号： H01B1/22 ,  H01L2224/81 ,  Y10T29/49117

    摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

    摘要翻译： 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。 通常，小于5微米的平均片尺寸适用于五微米互连。 然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量％。 纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

    Two signal one power plane circuit board
    10.
    发明授权
    Two signal one power plane circuit board 有权
    两个信号一个电源平面电路板

    公开(公告)号：US06204453B1

    公开(公告)日：2001-03-20

    申请号：US09203956

    申请日：1998-12-02

    申请人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    发明人： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

    IPC分类号： H05K103

    CPC分类号： H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0733

    摘要： A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers. Thereafter, the surfaces of the photoimageable material, vias and through holes are metalized by copper plating. This is preferably done by protecting the remainder of the circuitry with photoresist and utilizing photolithographic techniques. The photoresist is thereafter removed, leaving a circuit board or card having metalization on both sides, vias extending from both sides to the copper layer in the center, plated through holes connecting the two outer circuitized copper layers.

    摘要翻译： 形成印刷电路板或电路卡的方法设置有用作夹在一对可光成像的电介质层之间的电力平面的金属层。 光刻图形金属填充的通孔和光成像的电镀通孔位于光图案化材料中，信号电路位于每个介电材料的表面上，并连接到通孔和电镀通孔。 边界可以在板或卡周围，包括从电介质层之一的边缘终止的金属层。 铜箔上设有间隙孔。 可光成像的可固化介电材料的第一和第二层设置在作为可光成像的材料的铜的相对侧上。 图案在可光成象材料的第一层和第二层上显影，以通过通孔显露金属层。 在铜中的间隙孔处，通孔被开发成在两个电介质层中图案化孔。 此后，可光成像材料，通孔和通孔的表面通过镀铜进行金属化。 这优选通过用光致抗蚀剂和利用光刻技术保护电路的其余部分来实现。 然后去除光致抗蚀剂，留下在两侧具有金属化的电路板或卡，其中心的两侧延伸到铜层，通孔连接两个外部电路化的铜层。