公开(公告)号：US20160020163A1

公开(公告)日：2016-01-21

申请号：US14791670

申请日：2015-07-06

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

Abstract translation: 布线基板包括第一布线结构和第二布线结构。 第一布线结构包括覆盖第一布线层的第一绝缘层和通孔布线。 第一绝缘层的第一通孔填充有通孔布线。 第二布线结构包括第二布线层和第二绝缘层。 第二布线层形成在第一绝缘层的上表面和通孔布线的上端面上。 第二布线层部分地包括粗糙表面。 第二绝缘层堆叠在第一绝缘层的上表面上并覆盖第二布线层。 第二布线结构具有比第一布线结构更高的布线密度。 第二布线层的粗糙化表面的表面粗糙度比第一布线层小。

公开(公告)号：US20180166372A1

公开(公告)日：2018-06-14

申请号：US15866686

申请日：2018-01-10

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/11 ,  H01L23/00 ,  H05K3/46 ,  H01L25/10 ,  H01L25/065 ,  H01L23/538 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

公开(公告)号：US20170359891A1

公开(公告)日：2017-12-14

申请号：US15489876

申请日：2017-04-18

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yusuke GOZU ,  Yuta SAKAGUCHI ,  Noriyoshi SHIMIZU

IPC: H05K1/02 ,  H05K1/03 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0213 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H05K1/0353 ,  H05K3/002 ,  H05K3/0026 ,  H05K2201/0338 ,  H05K2203/0384

Abstract: A wiring substrate includes an insulating layer including a projection and a wiring layer on the projection. The wiring layer includes a first metal layer on an end face of the projection and a second metal layer on the first metal layer. The width of the end face of the projection is different from at least one of the width of the first metal layer and the width of the second metal layer. An inner wall surface and a bottom surface of a depression around the projection are roughened surfaces.

公开(公告)号：US20160007460A1

公开(公告)日：2016-01-07

申请号：US14790131

申请日：2015-07-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Akio ROKUGAWA

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/112 ,  H05K1/118 ,  H05K3/0038 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/025 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.

Abstract translation: 布线基板包括芯层，第一布线层，第一绝缘层，第一通孔布线，第二布线层，第二绝缘层，第二通孔布线，第三布线层，第三绝缘层，第三布线层 通过接线和通线。 通孔包括上端面和下端面。 上端面的面积比下端面的面积小。 第一绝缘层的上表面比第三绝缘层的下表面更平坦。 第二布线层具有比第一布线层的布线密度高的布线密度。