公开(公告)号：US20130328211A1

公开(公告)日：2013-12-12

申请号：US13910325

申请日：2013-06-05

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Akio ROKUGAWA ,  Akihiko TATEIWA ,  Masato TANAKA

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/81193 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers.

Abstract translation: 半导体器件包括半导体芯片，芯基板，第一和第二绝缘层以及第一和第二布线层。 绝缘层对金属的粘附性高于芯基板与金属的粘合性。 通孔在厚度方向上延伸穿过绝缘层。 通孔覆盖通孔的孔壁表面，沿着穿过绝缘层的厚度方向延伸，并且电连接第一和第二布线层。

公开(公告)号：US20150245473A1

公开(公告)日：2015-08-27

申请号：US14623689

申请日：2015-02-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Masato TANAKA ,  Toshinori KOYAMA ,  Akio ROKUGAWA

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/045 ,  H05K2201/09409 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09827 ,  H05K2201/10204 ,  H05K2201/10674 ,  Y10T29/49162 ,  H01L2924/00

Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.

Abstract translation: 布线基板包括第一布线结构，堆叠在第一布线结构的上表面上的第二布线结构和堆叠在第一布线结构的下表面上的最外绝缘层。 最外层绝缘层覆盖形成第一布线结构的布线层的底部布线层的一部分。 第二布线结构具有比第一布线结构高的布线密度。 体积比V1 / V2为0.8〜1.5，其中V1表示形成整个第二布线结构的布线层的体积，V2表示第一布线结构中底布线层的体积。

公开(公告)号：US20150062851A1

公开(公告)日：2015-03-05

申请号：US14469782

申请日：2014-08-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Wataru KANEDA ,  Hiromu ARISAKA ,  Akio ROKUGAWA

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/421 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K1/116 ,  H05K3/38 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/2072 ,  H05K2203/0789 ,  H01L2924/00

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract translation: 布线板包括涂覆第一布线层的第一绝缘层。 第一通孔在第一绝缘层的表面上开放，并露出第一布线层的表面。 布置在第一通孔中的第一通孔包括暴露于第一绝缘层的表面的端表面。 在第一通孔中的第一绝缘层和第一通孔之间形成间隙。 在第一绝缘层的表面和第一通孔的端面上堆叠第二布线层。 第二布线层包括填充间隙的垫。 该垫的平面形状大于第一通孔。

公开(公告)号：US20160007460A1

公开(公告)日：2016-01-07

申请号：US14790131

申请日：2015-07-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Akio ROKUGAWA

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/112 ,  H05K1/118 ,  H05K3/0038 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/025 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer.

Abstract translation: 布线基板包括芯层，第一布线层，第一绝缘层，第一通孔布线，第二布线层，第二绝缘层，第二通孔布线，第三布线层，第三绝缘层，第三布线层 通过接线和通线。 通孔包括上端面和下端面。 上端面的面积比下端面的面积小。 第一绝缘层的上表面比第三绝缘层的下表面更平坦。 第二布线层具有比第一布线层的布线密度高的布线密度。

公开(公告)号：US20140225275A1

公开(公告)日：2014-08-14

申请号：US14141765

申请日：2013-12-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Wataru KANEDA ,  Akio ROKUGAWA ,  Toshinori KOYAMA

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/76804 ,  H01L23/49822 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32235 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/00012

Abstract: A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.

Abstract translation: 布线基板包括：基底布线基板，包括第一布线层，第一布线层被埋置的第一绝缘层和在第一布线层下方形成的第一通孔;以及第二布线层，形成在第一绝缘层 并且通过第一通孔连接到第一布线层，以及重新布线部分，其包括形成在基布线基板上并具有形成在第一布线层上的第二通孔的第二绝缘层，以及重新布线层 形成在第二绝缘层上，并通过第二通孔连接到第一布线层。 再布线层由种子层和设置在种子层上的金属镀层形成，种子层的宽度等于或宽于金属镀层。

公开(公告)号：US20180166372A1

公开(公告)日：2018-06-14

申请号：US15866686

申请日：2018-01-10

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/11 ,  H01L23/00 ,  H05K3/46 ,  H01L25/10 ,  H01L25/065 ,  H01L23/538 ,  H05K1/09 ,  H05K3/00 ,  H05K3/38

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

公开(公告)号：US20150001738A1

公开(公告)日：2015-01-01

申请号：US14317529

申请日：2014-06-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Toshinori KOYAMA ,  Akio ROKUGAWA

IPC: H05K1/11 ,  H01L23/538 ,  H05K1/18 ,  H01L23/12

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/38 ,  H05K3/4007 ,  H05K3/4661 ,  H05K3/4673 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09563 ,  H05K2201/096 ,  H01L2924/00

Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.

Abstract translation: 布线板包括在第一绝缘层中的第一通孔，以露出第一布线层。 第一通孔中的第一通孔包括端面。 第一布线层设置在第一绝缘层和第一通孔的端面上。 第二绝缘层覆盖第二布线层。 第二绝缘层中的第二通孔露出第二布线层。 第二通路孔中的第二通孔布置在第一通孔的上方，穿过第二布线层。 第一绝缘层的外表面的表面粗糙度低于第一通孔的内表面。

公开(公告)号：US20140311771A1

公开(公告)日：2014-10-23

申请号：US14247355

申请日：2014-04-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Hitoshi SAKAGUCHI ,  Wataru KANEDA ,  Masato TANAKA ,  Akio ROKUGAWA

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/181 ,  H05K3/4007 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/025 ,  H01L2924/00

Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.

Abstract translation: 布线板依次包括在芯层上形成的第一绝缘层和第二绝缘层; 依次形成在芯层的另一表面上的第三绝缘层和阻焊层，分别形成在第一绝缘层和第二绝缘层中的第一布线层和第二布线层，其中第一绝缘层和第一绝缘层的第一端面 通过布线从最外侧的第一绝缘层的第一表面暴露出来，与最外层的第二布线层直接连接，第一通孔布线和最外层的第二布线层被分开地形成，最外面的第一绝缘层的第一表面和第一 第一通孔布线的端面是抛光表面，光滑的表面并且彼此齐平，并且第二布线层的布线密度高于第一布线层的布线密度。

公开(公告)号：US20130154102A1

公开(公告)日：2013-06-20

申请号：US13764532

申请日：2013-02-11

Applicant: FUJITSU LIMITED ,  SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Sadahiro KISHII ,  Tsuyoshi KANKI ,  Yoshihiro NAKATA ,  Yasushi KOBAYASHI ,  Masato TANAKA ,  Akio ROKUGAWA

IPC: H01L23/488

CPC classification number: H01L23/488 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Abstract translation: 支撑基板包括位于第一表面的高度之上的第一表面和第二表面。 芯片安装在第一个表面上。 第一绝缘膜设置在每个芯片上。 第一导电插头连接到延伸穿过每个第一绝缘膜的芯片。 由树脂填充的填充材料填充芯片之间的空间。 布线布置在第一绝缘膜和用于互连不同芯片的填充材料之上。 第二表面，第一绝缘膜的上表面和填充材料的上表面位于同一水平。

公开(公告)号：US20160020163A1

公开(公告)日：2016-01-21

申请号：US14791670

申请日：2015-07-06

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Noriyoshi SHIMIZU ,  Yusuke GOZU ,  Jun FURUICHI ,  Akio ROKUGAWA ,  Takashi Ito

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8149 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/095 ,  H05K1/111 ,  H05K1/112 ,  H05K1/114 ,  H05K1/115 ,  H05K3/0073 ,  H05K3/383 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/09845 ,  H05K2203/0392 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

Abstract translation: 布线基板包括第一布线结构和第二布线结构。 第一布线结构包括覆盖第一布线层的第一绝缘层和通孔布线。 第一绝缘层的第一通孔填充有通孔布线。 第二布线结构包括第二布线层和第二绝缘层。 第二布线层形成在第一绝缘层的上表面和通孔布线的上端面上。 第二布线层部分地包括粗糙表面。 第二绝缘层堆叠在第一绝缘层的上表面上并覆盖第二布线层。 第二布线结构具有比第一布线结构更高的布线密度。 第二布线层的粗糙化表面的表面粗糙度比第一布线层小。