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    Magnetic element with improved field response and fabricating method thereof
    1.
    发明授权
    Magnetic element with improved field response and fabricating method thereof 有权
    具有改善的场响应的磁性元件及其制造方法

    公开(公告)号：US06205052B1

    公开(公告)日：2001-03-20

    申请号：US09422447

    申请日：1999-10-21

    申请人： Jon Slaughter ,  Jing Shi ,  Eugene Chen ,  Saied Tehrani

    发明人： Jon Slaughter ,  Jing Shi ,  Eugene Chen ,  Saied Tehrani

    IPC分类号： G11C1115

    CPC分类号： H01L43/08 ,  B82Y25/00 ,  H01F10/324 ,  H01F10/3254 ,  H01F10/3268

    摘要： An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26). A second electrode (18) is included and comprises a free ferromagnetic layer (28). A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16). At least one additional layer (20 & 22) is provided between the base metal layer (13) and the spacer layer (16). The base metal layer (13) or at least one of the layers positioned between the base metal layer (13) and the spacer layer (16) having an x-ray amorphous structure such that a reduced topological coupling strength between the free ferromagnetic layer (28) and the fixed ferromagnetic layer (26) is achieved.

    摘要翻译： 一种用于磁性元件的改进和新颖的器件和制造方法，更具体地，包括第一电极（14），第二电极（18）和间隔层（16）的磁性元件（10）。 第一电极（14）包括固定的铁磁层（26）。 包括第二电极（18）并且包括自由铁磁层（28）。 间隔层（16）位于固定铁磁层（26）和自由铁磁（28）层间隔层（16）之间。 至少一个附加层（20和22）设置在基底金属层（13）和间隔层（16）之间。 基底金属层（13）或位于基底金属层（13）和间隔层（16）之间的层中的至少一层具有x射线非晶结构，使得游离铁磁层（ 28）和固定铁磁层（26）。

    MRAM having semiconductor device integrated therein
    2.
    发明授权
    MRAM having semiconductor device integrated therein 有权
    集成了半导体器件的MRAM

    公开(公告)号：US06285581B1

    公开(公告)日：2001-09-04

    申请号：US09460056

    申请日：1999-12-13

    申请人： Saied Tehrani ,  Jing Shi

    发明人： Saied Tehrani ,  Jing Shi

    IPC分类号： G11C1115

    CPC分类号： G11C11/15 ,  H01L27/224 ,  H01L27/228

    摘要： A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A magnetic layer (34) is positioned between the first ferromagnetic layer and a digit line (first) for pinning a magnetic vector within the second ferromagnetic layer. In a 13 embodiment, a gate contact (37) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.

    摘要翻译： 磁存储单元（10）具有位于形成p-n或肖特基结的第一（11）和第二（13）铁磁层之间的半导体层（12）。 磁性层（34）位于第一铁磁层和数字线（第一）之间，用于固定第二铁磁层内的磁矢量。 在13实施例中，栅极接触（37）与半导体材料层间隔开，用于控制通过半导体层的电子流。

    DEVICE AND METHOD FOR CALIBRATING RECIPROCITY ERRORS
    5.
    发明申请
    DEVICE AND METHOD FOR CALIBRATING RECIPROCITY ERRORS 审中-公开
    用于校准重复错误的装置和方法

    公开(公告)号：US20120314563A1

    公开(公告)日：2012-12-13

    申请号：US13578307

    申请日：2010-10-12

    申请人： Qinglin Luo ,  Jing Shi

    发明人： Qinglin Luo ,  Jing Shi

    IPC分类号： H04J3/14

    CPC分类号： H04B17/21 ,  H04B17/11 ,  H04B17/12 ,  H04B17/14 ,  H04L25/0212 ,  H04L25/0256

    摘要： The present invention provides a method for reciprocity error calibration, comprising steps of: measuring downlink channel response HDL; measuring uplink channel response HUL; calculating one of a user equipment reciprocity error Em and a base station reciprocity error Eb utilizing least square LS criterion based on the HDL and HUL in accordance with a reciprocity model HDL=Em−1HULTEb; calculating the other one of the Em and Eb based on the calculated one of Em and Eb utilizing an algorithm adopting minimum mean square error MMSE criterion; and performing a reciprocity error calibration operation utilizing the calculated user equipment reciprocity error Em and base station reciprocity error Eb. There is further provided a reciprocity error calibration device for performing the reciprocity error calibration method. The reciprocity error calibration method and the reciprocity error calibration device according to the present invention may provide better reciprocity error calibration performance.

    摘要翻译： 本发明提供了一种用于互易误差校准的方法，包括以下步骤：测量下行链路信道响应HDL; 测量上行链路信道响应HUL; 使用基于HDL和HUL的最小二乘LS准则，根据互易模型HDL = Em-1HULTEb计算用户设备互易误差Em和基站互易误差Eb之一; 使用采用最小均方误差MMSE准则的算法，基于Em和Eb中的一个计算Em和Eb中的另一个; 以及利用所计算的用户设备互易误差Em和基站互易误差Eb来执行互易误差校准操作。 还提供了一种用于执行互易误差校准方法的互易误差校准装置。 根据本发明的互易误差校准方法和互易误差校准装置可以提供更好的互易误差校准性能。

    PREPARATION METHODS OF 6-SUBSTITUTED AMINO-3-CYANOQUINOLINE COMPOUNDS AND THE INTERMEDIATES THEREOF
    6.
    发明申请
    PREPARATION METHODS OF 6-SUBSTITUTED AMINO-3-CYANOQUINOLINE COMPOUNDS AND THE INTERMEDIATES THEREOF 有权
    6-取代的氨基-3-氰基喹啉化合物的制备方法及其中间体

    公开(公告)号：US20110263860A1

    公开(公告)日：2011-10-27

    申请号：US13125721

    申请日：2009-10-23

    申请人： Yongjun Mao ,  Jianfeng Li ,  Jin Zheng ,  Zheng Liu ,  Kai Xie ,  Haihong Li ,  Jing Shi ,  Ye Li ,  Jingshan Shen

    发明人： Yongjun Mao ,  Jianfeng Li ,  Jin Zheng ,  Zheng Liu ,  Kai Xie ,  Haihong Li ,  Jing Shi ,  Ye Li ,  Jingshan Shen

    IPC分类号： C07D215/20 ,  C07D215/38 ,  C07C69/78

    CPC分类号： C07C229/64 ,  C07C237/30 ,  C07C255/30 ,  C07D215/56

    摘要： The present invention relates to a method for preparing 6-substituted amino-3-cyanoquinoline compounds (compound A for short) and the intermediates thereof, more particularly, to a compound of the following formula (I), the preparation method thereof, the intermediates thereof and use thereof for preparing the compound A. The compound of the formula (I) is cyclized in the presence of an alkali to give a compound of formula A, wherein W is OH; or the compound of the formula (I) is cyclized in the presence of an alkali, and then chlorinated to give a compound of the formula A, wherein W is Cl. Compared with the known methods in the literature, the method for preparing the compound A from the compound of formula (I) according to the present invention can avoid using high-temperature condition and high boiling point solvents, and is safe and environment-friendly, mild in reaction condition, easy in operation with a high yield and high product purity.

    摘要翻译： 本发明涉及一种制备6-取代氨基-3-氰基喹啉化合物（简称为化合物A）的方法及其中间体，更具体地涉及下式（I）的化合物，其制备方法，中间体 及其用于制备化合物A的用途。式（I）化合物在碱存在下环化，得到式A化合物，其中W为OH; 或式（I）化合物在碱的存在下环化，然后氯化，得到式A化合物，其中W为Cl。 与文献中已知的方法相比，本发明的式（I）化合物制备化合物A的方法可以避免使用高温条件和高沸点溶剂，且安全环保， 反应条件温和，易于操作，产率高，产品纯度高。

    SiGe HBT and method of manufacturing the same
    7.
    发明授权
    SiGe HBT and method of manufacturing the same 有权
    SiGe HBT及其制造方法

    公开(公告)号：US09012279B2

    公开(公告)日：2015-04-21

    申请号：US13613236

    申请日：2012-09-13

    申请人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

    发明人： Donghua Liu ,  Wenting Duan ,  Wensheng Qian ,  Jun Hu ,  Jing Shi

    IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7371

    摘要： A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.

    摘要翻译： 公开了一种SiGe HBT，其包括：硅衬底; 形成在硅衬底中的浅沟槽场氧化物; 形成在每个浅沟槽场氧化物的底部的伪掩埋层; 形成在所述硅衬底的表面下方的集电极区域，所述集电极区域夹在所述浅沟槽场氧化物之间和所述伪埋层之间; 形成在每个浅沟槽场氧化物上方的多晶硅栅极，其厚度大于150nm; 多晶硅栅极和集电极区域上的基极区域; 发射极区隔离氧化物; 并且发射极区域上的发射极区域隔离氧化物和基极区域的一部分。 多晶硅栅极通过CMOS工艺中的MOSFET的栅极多晶硅工艺形成。 还公开了制造SiGe HBT的方法。

    Self-locking features in a multi-chip module
    8.
    发明授权
    Self-locking features in a multi-chip module 有权
    多芯片模块中的自锁功能

    公开(公告)号：US08315065B2

    公开(公告)日：2012-11-20

    申请号：US12568017

    申请日：2009-09-28

    申请人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

    发明人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

    IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

    CPC分类号： H05K3/303 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/09036 ,  H05K2201/1059 ,  H05K2201/209 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

    摘要： A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.

    摘要翻译： 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征可重新机械耦合。 这些积极和消极的特征可以彼此交配和自锁。 例如，其中一个表面上的阳性特征可以包括成对的相对的微弹簧，并且负特征可以包括在另一个表面上的凹坑或凹槽。 当基板机械耦合时，给定的一对正特征可以在另一表面的平面中提供力。 此外，通过压缩MCM使得基板的表面彼此推动，可以释放机械联接。

    SELF-LOCKING FEATURES IN A MULTI-CHIP MODULE
    10.
    发明申请
    SELF-LOCKING FEATURES IN A MULTI-CHIP MODULE 有权
    多芯片模块中的自锁特性

    公开(公告)号：US20110075380A1

    公开(公告)日：2011-03-31

    申请号：US12568017

    申请日：2009-09-28

    申请人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

    发明人： Jing Shi ,  Hiren D. Thacker ,  Ashok V. Krishnamoorthy

    IPC分类号： H05K1/14 ,  H05K3/36

    CPC分类号： H05K3/303 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/325 ,  H05K2201/0311 ,  H05K2201/09036 ,  H05K2201/1059 ,  H05K2201/209 ,  H05K2203/167 ,  Y02P70/613 ,  Y10T29/49126 ,  H01L2924/00

    摘要： A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. For example, the positive features on one of the surfaces may include pairs of counterposed micro-springs, and the negative features may include pits or grooves on the other surface. When the substrates are mechanically coupled, a given pair of positive features may provide a force in a plane of the other surface. Furthermore, by compressing the MCM so that the surfaces of the substrates are pushed toward each other, the mechanical coupling may be released.

    摘要翻译： 描述了多芯片模块（MCM）。 该MCM包括至少两个基板，其通过在基板的相对表面上的正和负特征可重新机械耦合。 这些积极和消极的特征可以彼此交配和自锁。 例如，其中一个表面上的阳性特征可以包括成对的相对的微弹簧，并且负特征可以包括在另一个表面上的凹坑或凹槽。 当基板机械耦合时，给定的一对正特征可以在另一表面的平面中提供力。 此外，通过压缩MCM使得基板的表面彼此推动，可以释放机械联接。