公开(公告)号：US20140151744A1

公开(公告)日：2014-06-05

申请号：US14093126

申请日：2013-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo LEE ,  Seong-woon BOOH

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L23/49844 ,  H01L23/3735 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/072 ,  H01L25/18 ,  H01L29/2003 ,  H01L29/7393 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05113 ,  H01L2224/05116 ,  H01L2224/05117 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05138 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05149 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05163 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05183 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2224/85801 ,  H01L2224/8584 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01072 ,  H01L2924/01052 ,  H01L2924/014 ,  H01L2224/83205

Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.

Abstract translation: 功率半导体器件可以包括：下部结构; 下部结构上的焊料层; 焊料层上的半导体结构; 半导体结构上的接触层; 接触层上的垫层; 和/或垫层和下部结构之间的线。 焊料层可以电连接到半导体结构的第一电极。

公开(公告)号：US20170331209A1

公开(公告)日：2017-11-16

申请号：US15666745

申请日：2017-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Che-heung KIM ,  Chang-sik KIM ,  Seong-woon BOOH

IPC: H01R12/70 ,  H01L25/07 ,  H02M7/00

CPC classification number: H01R12/7088 ,  H01L25/072 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M7/003 ,  H01L2924/00

Abstract: According to example embodiments, a substrate for a power module includes first to third parts spaced apart from each other, where the third part surrounds the first and second parts, and a conductive layer on the first to third parts. A terminal of a first polarity is connected to the first part, and a terminal of a second polarity is connected to the second part. The first and second terminals may be spaced apart from each other and each have a coupling part, a body, and a contact part. The bodies of the first and second terminals may overlap each other. A power module may include the substrate.

公开(公告)号：US20150115452A1

公开(公告)日：2015-04-30

申请号：US14311708

申请日：2014-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Won YOON ,  Baik-woo LEE ,  Seong-woon BOOH ,  Chang-mo JEONG

IPC: H01L23/00 ,  B23K1/00

CPC classification number: H01L24/29 ,  B23K1/0016 ,  B23K20/023 ,  B23K20/16 ,  B23K20/233 ,  B23K35/0244 ,  B23K35/025 ,  B23K2101/42 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/95 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2732 ,  H01L2224/29083 ,  H01L2224/29139 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/33181 ,  H01L2224/83091 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/83905 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/83

Abstract: Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.

Abstract translation: 提供半导体器件封装和制造半导体器件封装的方法。 半导体器件封装可以包括在衬底和半导体芯片之间的结合层，并且结合层可以包括金属间化合物。 金属间化合物可以是金属和焊料材料的化合物。 金属间化合物可以包括Ag 3 Sn。 制造半导体器件封装的方法可以包括通过使用包括金属颗粒和焊料材料的混合膏形成将半导体芯片与基板结合的接合层。 接合层可以通过形成金属间化合物而形成，该金属间化合物是通过加热混合的糊料使金属颗粒与焊料材料反应形成的。

公开(公告)号：US20150001726A1

公开(公告)日：2015-01-01

申请号：US14087472

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo LEE ,  Seong-woon BOOH

IPC: H01L29/45 ,  H01L27/04

CPC classification number: H01L27/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L29/861 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48855 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83203 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/83951 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/83205

Abstract: A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

Abstract translation: 功率半导体模块包括基板上的第一功率器件，第一功率器件的上表面上的第一电极，第一电极上的第一镀镍层和连接到第一镀镍层的铜线。

公开(公告)号：US20140120774A1

公开(公告)日：2014-05-01

申请号：US13920732

申请日：2013-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Che-Heung KIM ,  Young-hun BYUN ,  Seong-woon BOOH

IPC: H01L31/05

CPC classification number: H01L31/0504 ,  H01L23/3735 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/30107 ,  Y02E10/50 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided are a substrate for a power module having a uniform parallel switching characteristic and a power module including the same. The substrate for the power module includes a plurality of areas on which input terminals are mounted, an area on which an output terminal is mounted, a plurality of areas on which devices are mounted, and an area on which a plurality of control pins are mounted. The plurality of areas on which the devices are mounted are bilaterally symmetric about the area on which the plurality of control pins are mounted. The plurality of areas on which the input terminals are mounted, respectively, are provided into three areas spaced apart from each other and bilaterally symmetric to each other. The plurality of areas on which the device are mounted are bilaterally symmetric about the area on which the control pins are mounted.

Abstract translation: 提供具有均匀并联开关特性的功率模块的基板和包括该基板的功率模块。 用于功率模块的基板包括安装有输入端子的多个区域，安装有输出端子的区域，安装有设备的多个区域以及安装有多个控制引脚的区域 。 安装有这些装置的多个区域是关于多个控制销安装在其上的区域的左右对称的。 分别安装有输入端子的多个区域被设置为彼此间隔开并彼此双边对称的三个区域。 安装设备的多个区域关于安装控制销的区域是双边对称的。

公开(公告)号：US20140021620A1

公开(公告)日：2014-01-23

申请号：US13739372

申请日：2013-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baik-woo LEE ,  Young-hun BYUN ,  Seong-woon BOOH ,  Chang-mo JEONG

IPC: H01L23/498 ,  H01L21/02

CPC classification number: H01L23/49866 ,  H01L21/02697 ,  H01L23/3735 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/0508 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48864 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/01322 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Abstract translation: 根据本发明构思的示例实施例，功率器件包括具有面向第二表面的第一表面，上电极和下电极的半导体结构。 上电极可以包括在半导体结构的第一表面上的第一接触层和位于第一接触层上并由含镍（Ni）的金属形成的第一接合焊盘层。 下部电极可以包括在半导体结构的第二表面下方的第二接触层和位于第二接触层下方并由含有Ni的金属形成的第二接合焊盘层。