Patent search ap:("Samsung Electronics Co. Page Ltd.") AND inv:"Baik-woo LEE"

1.

发明申请
SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE INCLUDING ELECTROMAGNETIC WAVE SHIELD LAYER 审中-公开
Title translation: 半导体封装和半导体器件，包括电磁波屏蔽层

公开(公告)号：US20160276288A1

公开(公告)日：2016-09-22

申请号：US14960443

申请日：2015-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo LEE , Young-jae KIM

IPC: H01L23/552 , H01L23/31

CPC classification number: H01L23/552 , H01L23/3121 , H01L24/45 , H01L24/97 , H01L2224/16227 , H01L2224/32225 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45157 , H01L2224/45164 , H01L2224/45166 , H01L2224/45169 , H01L2224/45171 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/15311 , H01L2924/3025 , H01L2924/00012 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2224/81

Abstract: A semiconductor package is provided with an electromagnetic wave shielding layer, and a conductive ground layer connected thereto. For example, in certain embodiments, the conductive ground layer is formed in a package substrate of the semiconductor package. The conductive ground layer may include a planar, or base portion, and a protruding, or lip portion. The planar or base portion as well as the protruding or lip portion may contact the electromagnetic wave shielding layer surrounding the semiconductor package.

Abstract translation: 半导体封装设置有电磁波屏蔽层和与其连接的导电接地层。例如，在某些实施例中，导电接地层形成在半导体封装的封装衬底中。导电接地层可以包括平面或基部，以及突出或唇部。平面或基部以及突出部分或唇部可接触围绕半导体封装的电磁波屏蔽层。

2.

发明申请
MAGNETO-RESISTIVE CHIP PACKAGE INCLUDING SHIELDING STRUCTURE 审中-公开

公开(公告)号：US20180375017A1

公开(公告)日：2018-12-27

申请号：US16121266

申请日：2018-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-gwon JANG , Baik-woo LEE , Young-jae KIM

IPC: H01L43/08 , H01L23/051 , H01L23/055 , H01L23/06 , H01L23/10 , H01L23/14 , H01L23/29 , H01L23/00 , H01L23/31 , H01L23/552 , H01L23/049 , H01L43/12

Abstract: In one embodiment, a magneto-resistive chip package includes a circuit board; a shielding body including a shielding base part positioned on the circuit board and a shielding intermediate part extending from one side of the shielding base part; a magneto-resistive chip positioned on the shielding base part and including a magneto-resistive cell array; an internal connection part electrically connecting the magneto-resistive chip to the circuit board; an encapsulation part encapsulating the magneto-resistive chip on the circuit board, and having an upper surface that is higher than an upper surface of the magneto-resistive chip; and a shielding cover positioned on the shielding intermediate part, and on the encapsulation part.

3.

发明申请
NITRIDE SEMICONDUCTOR BASED POWER CONVERTING DEVICE 有权
Title translation: 基于氮化物半导体的功率转换器件

公开(公告)号：US20140091311A1

公开(公告)日：2014-04-03

申请号：US13921466

申请日：2013-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo-chul JEON , Baik-woo LEE , Jai-kwang SHIN , Jae-joon OH

IPC: H01L29/205

CPC classification number: H01L29/205 , H01L21/2654 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L28/10 , H01L28/20 , H01L29/0642 , H01L29/2003 , H01L29/7786 , H01L29/86 , H01L29/94

Abstract: A nitride semiconductor based power converting device includes a nitride semiconductor based power transistor, and at least one nitride semiconductor based passive device. The passive device and the power transistor respectively include a channel layer including a first nitride semiconductor material, and a channel supply layer on the channel layer including a second nitride semiconductor material to induce a 2-dimensional electron gas (2DEG) at the channel layer. The passive device may be a resistor, an inductor, or a capacitor.

Abstract translation: 一种基于氮化物半导体的功率转换器件包括基于氮化物半导体的功率晶体管和至少一个氮化物半导体的无源器件。无源器件和功率晶体管分别包括包括第一氮化物半导体材料的沟道层和在沟道层上的沟道供应层，该沟道层包括在沟道层处引起二维电子气（2DEG）的第二氮化物半导体材料。无源器件可以是电阻器，电感器或电容器。

4.

发明申请
POWER DEVICE AND POWER DEVICE MODULE 有权
Title translation: 电源设备和电源设备模块

公开(公告)号：US20140021620A1

公开(公告)日：2014-01-23

申请号：US13739372

申请日：2013-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baik-woo LEE , Young-hun BYUN , Seong-woon BOOH , Chang-mo JEONG

IPC: H01L23/498 , H01L21/02

CPC classification number: H01L23/49866 , H01L21/02697 , H01L23/3735 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/03424 , H01L2224/03464 , H01L2224/0508 , H01L2224/05644 , H01L2224/05664 , H01L2224/06181 , H01L2224/291 , H01L2224/29139 , H01L2224/32225 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/73265 , H01L2224/8384 , H01L2224/85444 , H01L2224/85447 , H01L2924/01322 , H01L2924/13033 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/15787 , H01L2924/3011 , H01L2924/3511 , H01L2924/014 , H01L2924/00012 , H01L2924/00 , H01L2924/00014

Abstract: According to example embodiments of inventive concepts, a power device includes a semiconductor structure having a first surface facing a second surface, an upper electrode, and a lower electrode. The upper electrode may include a first contact layer that is on the first surface of the semiconductor structure, and a first bonding pad layer that is on the first contact layer and is formed of a metal containing nickel (Ni). The lower electrode may include a second contact layer that is under the second surface of the semiconductor structure, and a second bonding pad layer that is under the second contact layer and is formed of a metal containing Ni.

Abstract translation: 根据本发明构思的示例实施例，功率器件包括具有面向第二表面的第一表面，上电极和下电极的半导体结构。上电极可以包括在半导体结构的第一表面上的第一接触层和位于第一接触层上并由含镍（Ni）的金属形成的第一接合焊盘层。下部电极可以包括在半导体结构的第二表面下方的第二接触层和位于第二接触层下方并由含有Ni的金属形成的第二接合焊盘层。

5.

发明申请
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME 有权
Title translation: 半导体器件封装及其制造方法

公开(公告)号：US20150115452A1

公开(公告)日：2015-04-30

申请号：US14311708

申请日：2014-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Won YOON , Baik-woo LEE , Seong-woon BOOH , Chang-mo JEONG

IPC: H01L23/00 , B23K1/00

CPC classification number: H01L24/29 , B23K1/0016 , B23K20/023 , B23K20/16 , B23K20/233 , B23K35/0244 , B23K35/025 , B23K2101/42 , H01L24/32 , H01L24/33 , H01L24/83 , H01L24/95 , H01L24/97 , H01L2224/04026 , H01L2224/05568 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/2732 , H01L2224/29083 , H01L2224/29139 , H01L2224/293 , H01L2224/29339 , H01L2224/29499 , H01L2224/32225 , H01L2224/32503 , H01L2224/32507 , H01L2224/33181 , H01L2224/83091 , H01L2224/83097 , H01L2224/83192 , H01L2224/83203 , H01L2224/8382 , H01L2224/83825 , H01L2224/8383 , H01L2224/8384 , H01L2224/83905 , H01L2224/97 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2224/83

Abstract: Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag3Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.

Abstract translation: 提供半导体器件封装和制造半导体器件封装的方法。半导体器件封装可以包括在衬底和半导体芯片之间的结合层，并且结合层可以包括金属间化合物。金属间化合物可以是金属和焊料材料的化合物。金属间化合物可以包括Ag 3 Sn。制造半导体器件封装的方法可以包括通过使用包括金属颗粒和焊料材料的混合膏形成将半导体芯片与基板结合的接合层。接合层可以通过形成金属间化合物而形成，该金属间化合物是通过加热混合的糊料使金属颗粒与焊料材料反应形成的。

6.

发明申请
POWER SEMICONDUCTOR MODULE 审中-公开
Title translation: 功率半导体模块

公开(公告)号：US20150001726A1

公开(公告)日：2015-01-01

申请号：US14087472

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo LEE , Seong-woon BOOH

IPC: H01L29/45 , H01L27/04

CPC classification number: H01L27/04 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L29/861 , H01L2224/04042 , H01L2224/05124 , H01L2224/05655 , H01L2224/0603 , H01L2224/29101 , H01L2224/29339 , H01L2224/29347 , H01L2224/32225 , H01L2224/45015 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4846 , H01L2224/48472 , H01L2224/48855 , H01L2224/4903 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L2224/83203 , H01L2224/83801 , H01L2224/8384 , H01L2224/83951 , H01L2224/85205 , H01L2924/00011 , H01L2924/10272 , H01L2924/1033 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15747 , H01L2924/00014 , H01L2924/00 , H01L2924/2076 , H01L2924/01015 , H01L2924/01005 , H01L2924/00012 , H01L2924/014 , H01L2224/83205

Abstract: A power semiconductor module includes a first power device on a substrate, a first electrode on an upper surface of the first power device, a first nickel plating layer on the first electrode, and a copper wire connected to the first nickel plating layer.

Abstract translation: 功率半导体模块包括基板上的第一功率器件，第一功率器件的上表面上的第一电极，第一电极上的第一镀镍层和连接到第一镀镍层的铜线。

7.

发明申请
PRINTED CIRCUIT BOARD AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME 有权
Title translation: 印刷电路板和包括相同的半导体封装

公开(公告)号：US20170064824A1

公开(公告)日：2017-03-02

申请号：US15232794

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jae KIM , Hyung-gil BAEK , Baik-woo LEE

IPC: H05K1/11 , H05K3/22 , H05K3/40 , H05K1/18 , H05K3/00

CPC classification number: H05K1/0219 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H05K1/111 , H05K1/183 , H05K3/0073 , H05K3/22 , H05K3/3452 , H05K3/4007 , H05K2201/0373 , H05K2201/0376 , H05K2201/09409 , H05K2201/09745 , H05K2201/0989 , H05K2203/1105 , Y02P70/611 , H01L2924/00012 , H01L2924/00014

Abstract: A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.

Abstract translation: 提供印刷电路板。印刷电路板包括基底基板，该基板在其上表面上包括芯片安装区域，芯片安装区域中的多个连接焊盘结构以及基板上的延伸图案，与两个相邻的连接焊盘结构中的每一个间隔开在多个连接焊盘结构中，并且沿着两个相邻的连接焊盘结构延伸。多个连接垫结构的上表面位于比延伸图案的上表面更高的水平。

8.

发明申请
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权
Title translation: 半导体封装及其制造方法

公开(公告)号：US20160099218A1

公开(公告)日：2016-04-07

申请号：US14815937

申请日：2015-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baik-woo LEE , Dong-hun LEE , Jae-gwon JANG , Chul-yong JANG

IPC: H01L23/552 , H01L21/78 , B29C70/78 , H01L21/56

CPC classification number: H01L23/552 , B29C70/78 , B29K2063/00 , B29L2009/005 , B29L2031/3481 , H01L21/561 , H01L21/565 , H01L21/78 , H01L24/97 , H01L25/0652 , H01L25/18 , H01L2224/16227 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2924/15313 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2224/81 , H01L2224/85

Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

Abstract translation: 提供一种半导体封装的制造方法。该方法包括将半导体器件安装在衬底上; 在基板上设置模具，其中模具形成为覆盖半导体器件，使得模具的至少一个内侧表面具有斜面; 将模塑材料提供到模具中以封装半导体器件; 从基板上取出模具; 以及形成电磁屏蔽（EMS）层以覆盖模制材料的顶表面和侧表面。