公开(公告)号：US20140091308A1

公开(公告)日：2014-04-03

申请号：US13631534

申请日：2012-09-28

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz KABEHIE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

摘要翻译： 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20140091360A1

公开(公告)日：2014-04-03

申请号：US13630527

申请日：2012-09-28

申请人： Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

发明人： Ravi PILLARISETTY ,  Seung Hoon SUNG ,  Niti GOEL ,  Jack T. KAVALIEROS ,  Sansaptak DASGUPTA ,  Van H. LE ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Gilbert DEWEY ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Robert S. CHAU

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L21/845 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

摘要翻译： 沟槽限制的选择性外延生长工艺，其中半导体器件层的外延生长在沟槽的范围内进行。 在实施例中，制造沟槽以包括设置在沟槽底部的原始平面半导体晶种表面。 接种表面周围的半导体区域可以相对于接种表面凹陷，其中隔离电介质设置在其上以包围半导体晶种层并形成沟槽。 在形成沟槽的实施例中，牺牲性硬掩模翅片可以被覆盖在电介质中，然后将其平坦化以暴露硬掩模翅片，然后将其去除以暴露接种表面。 通过选择性异质外延从种子表面形成半导体器件层。 在实施例中，通过使隔离电介质的顶表面凹陷，从半导体器件层形成非平面器件。 在实施例中，可以从半导体器件层制造具有高载流子迁移率的非平面器件CMOS器件。

公开(公告)号：US20140094223A1

公开(公告)日：2014-04-03

申请号：US13631514

申请日：2012-09-28

申请人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU

发明人： Sansaptak DASGUPTA ,  Han Wui THEN ,  Niloy MUKHERJEE ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

摘要翻译： 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

公开(公告)号：US20140170998A1

公开(公告)日：2014-06-19

申请号：US13720852

申请日：2012-12-19

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC分类号： H01L29/80 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20140175515A1

公开(公告)日：2014-06-26

申请号：US13725546

申请日：2012-12-21

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Robert S. CHAU

IPC分类号： H01L29/772 ,  H01L29/66

CPC分类号： H01L29/78696 ,  H01L21/02387 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/02538 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66409 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/772 ,  H01L29/785 ,  H01L29/78681

摘要： A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

摘要翻译： III-N半导体通道在过渡层和III-N偏振层之间组成分级。 在实施例中，栅堆叠沉积在包括渐变III-N半导体沟道的鳍的侧壁上，允许在响应于栅极偏置电压的至少两个侧壁表面相邻的III-N半导体沟道中形成传输沟道。 在实施例中，栅极叠层完全沉积在包括III-N半导体沟道的纳米线周围，该纳米线被组成分级，以使得能够响应于栅极形成与偏振层和过渡层两者相邻的III-N半导体沟道中的传输沟道 偏压。

公开(公告)号：US20140091845A1

公开(公告)日：2014-04-03

申请号：US13631569

申请日：2012-09-28

申请人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Gerhard SCHROM ,  Valluri R. RAO ,  Robert S. CHAU

发明人： Han Wui THEN ,  Sansaptak DASGUPTA ,  Gerhard SCHROM ,  Valluri R. RAO ,  Robert S. CHAU

IPC分类号： H01L29/94 ,  H03K3/00 ,  H01L21/8232

CPC分类号： H01L27/0605 ,  H01L27/0805 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/93 ,  H01L29/94

摘要： III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

摘要翻译： 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：US20140084387A1

公开(公告)日：2014-03-27

申请号：US13627971

申请日：2012-09-26

申请人： Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

发明人： Gilbert DEWEY ,  Robert S. CHAU ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Scott B. CLENDENNING ,  Ravi PILLARISETTY

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

摘要： A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

摘要翻译： 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US20140084398A1

公开(公告)日：2014-03-27

申请号：US13627968

申请日：2012-09-26

申请人： Kaan OGUZ ,  Mark L. DOCZY ,  Brian DOYLE ,  Uday SHAH ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Robert S. CHAU

发明人： Kaan OGUZ ,  Mark L. DOCZY ,  Brian DOYLE ,  Uday SHAH ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Robert S. CHAU

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

摘要翻译： 适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。 在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

公开(公告)号：US20090261391A1

公开(公告)日：2009-10-22

申请号：US12493291

申请日：2009-06-29

申请人： Jack KAVALIEROS ,  Annalisa CAPPELLANI ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew V. METZ ,  Suman DATTA ,  Chris E. BARNS ,  Robert S. CHAU

发明人： Jack KAVALIEROS ,  Annalisa CAPPELLANI ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew V. METZ ,  Suman DATTA ,  Chris E. BARNS ,  Robert S. CHAU

IPC分类号： H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/28079 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7834

摘要： A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.

摘要翻译： 互补金属氧化物半导体集成电路可以形成有使用替换金属栅极和升高源极漏极形成的PMOS器件。 凸起的源极漏极可以由掺杂p型的外延沉积的硅锗材料形成。 替代金属栅极工艺导致金属栅电极，并且可能涉及去除氮化物蚀刻停止层。