Patent search ap:("Taiwan Semiconductor Manufacturing Company Page Ltd.") AND inv:"Tzu-Yu Wang"

1.

发明授权
Cylindrical embedded capacitors 有权

公开(公告)号：US09691840B2

公开(公告)日：2017-06-27

申请号：US14132563

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng

IPC: H01L21/00 , H01L49/02 , H01L21/768 , H01L23/48 , H01L23/00

CPC classification number: H01L28/40 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L28/92 , H01L2224/0401 , H01L2224/05008 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

2.

发明申请
Cylindrical Embedded Capacitors 审中-公开
Title translation: 圆柱嵌入式电容器

公开(公告)号：US20140106536A1

公开(公告)日：2014-04-17

申请号：US14132563

申请日：2013-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： An-Jhih Su , Chi-Chun Hsieh , Tzu-Yu Wang , Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Wen-Chih Chiou , Shin-Puu Jeng

IPC: H01L49/02 , H01L21/768

CPC classification number: H01L28/40 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/14 , H01L28/92 , H01L2224/0401 , H01L2224/05008 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/131 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract translation: 一种装置包括具有与前表面相对的前表面和后表面的基底。电容器形成在衬底中，并包括第一电容器板; 围绕所述第一电容器板的第一绝缘层; 以及环绕所述第一绝缘层的第二电容器板。第一电容器板，第一绝缘层和第二电容器板中的每一个从基板的前表面延伸到后表面。

3.

发明授权
Interposer test structures and methods 有权

公开(公告)号：US10090213B2

公开(公告)日：2018-10-02

申请号：US15449683

申请日：2017-03-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng

IPC: H01L21/48 , H01L21/66 , H01L23/498 , H01L23/58 , G01R1/073

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

4.

发明申请
Interposer Test Structures and Methods 审中-公开
Title translation: 插件测试结构和方法

公开(公告)号：US20150380324A1

公开(公告)日：2015-12-31

申请号：US14846605

申请日：2015-09-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng

IPC: H01L21/66 , H01L23/58 , H01L23/522 , H01L23/498

CPC classification number: H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract translation: 本公开的实施例是包括插入器的结构。插入器具有沿着插入件的周边延伸的测试结构，并且测试结构的至少一部分处于第一再分配元件中。第一再分配元件位于中介层的衬底的第一表面上。测试结构是中间的并且电耦合到至少两个探针焊盘。

5.

发明申请
Clustering for Prediction Models in Process Control and for Optimal Dispatching 审中-公开
Title translation: 过程控制和最优调度中预测模型的聚类

公开(公告)号：US20150241876A1

公开(公告)日：2015-08-27

申请号：US14706768

申请日：2015-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Cheng Ko , Tzu-Yu Wang , Kewei Zuo , Kuan Teng Lo , Chien Rhone Wang , Chih-Wei Lai

IPC: G05B19/418

CPC classification number: G05B19/41885 , G05B17/02 , G05B2219/45032

Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

Abstract translation: 第一实施例是一种用于半导体处理控制的方法，其包括基于处理数据将处理级的处理工具集群到工具集群中，并且基于工具集群形成用于处理半导体晶片的预测模型。第二实施例是一种用于半导体处理控制的方法，包括提供第一级工具集群和第二级工具集群之间的集群路由，为每个集群路由分配比较优化等级，以及调度晶片的处理。比较优化排名确定了哪些集群路由提供高晶圆处理均匀性。此外，需要高晶圆处理均匀性的晶片被调度为沿着具有高比较优化等级的一个集群路由进行处理，该优先等级标识一个集群路由以具有最高的晶片处理均匀性，并且不需要高晶片处理均匀性的晶片是计划沿着另一个集群路由处理。

6.

发明申请
Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods 有权
Title translation: 半导体器件设计方法和导电凸块图案增强方法

公开(公告)号：US20150143324A1

公开(公告)日：2015-05-21

申请号：US14084813

申请日：2013-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng

IPC: G06F17/50

CPC classification number: G06F17/5077 , G06F17/5009 , G06F17/5081 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , H01L24/11 , H01L24/13 , H01L2224/13005 , H01L2224/16227 , H01L2924/15311

Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.

Abstract translation: 公开了半导体器件设计方法和导电凸块图案增强方法。在一些实施例中，设计半导体器件的方法包括设计导电凸块图案设计，以及在导电凸块图案设计上实现导电凸块图案增强算法以创建增强的导电凸块图案设计。基于增强的导电凸块图案设计设计布线图案。在路由模式上执行设计规则检查（DRC）过程。

7.

发明授权
Clustering for prediction models in process control and for optimal dispatching 有权

公开(公告)号：US10054938B2

公开(公告)日：2018-08-21

申请号：US14706768

申请日：2015-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung Cheng Ko , Tzu-Yu Wang , Kewei Zuo , Kuan Teng Lo , Chien Rhone Wang , Chih-Wei Lai

IPC: G05B17/02 , G05B15/02 , G05B19/418

CPC classification number: G05B19/41885 , G05B17/02 , G05B2219/45032

Abstract: A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route.

8.

发明授权
Semiconductor device design methods and conductive bump pattern enhancement methods 有权
Title translation: 半导体器件设计方法和导电凸块图案增强方法

公开(公告)号：US09372951B2

公开(公告)日：2016-06-21

申请号：US14084813

申请日：2013-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng

IPC: G06F17/50

CPC classification number: G06F17/5077 , G06F17/5009 , G06F17/5081 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , H01L24/11 , H01L24/13 , H01L2224/13005 , H01L2224/16227 , H01L2924/15311

Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.

Abstract translation: 公开了半导体器件设计方法和导电凸块图案增强方法。在一些实施例中，设计半导体器件的方法包括设计导电凸块图案设计，以及在导电凸块图案设计上实现导电凸块图案增强算法以创建增强的导电凸块图案设计。基于增强的导电凸块图案设计设计布线图案。在路由模式上执行设计规则检查（DRC）过程。