公开(公告)号：US07102367B2

公开(公告)日：2006-09-05

申请号：US10621445

申请日：2003-07-18

申请人： Yasuo Yamagishi ,  Takeshi Shioga ,  John David Baniecki ,  Kazuaki Kurihara

发明人： Yasuo Yamagishi ,  Takeshi Shioga ,  John David Baniecki ,  Kazuaki Kurihara

IPC分类号： G01R31/02 ,  H01R13/00 ,  G01R31/26 ,  H01L29/08

CPC分类号： G01R1/07378 ,  G01R31/2886 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

摘要： A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.

摘要翻译： 探针卡包括探针，在其中具有多层互连结构的堆积互连层，并且在与多层互连结构电连接的顶表面上承载探针，以及设置在积层互连层上的电容器，其与 通过多层互连结构的探针中的一个，其中多层互连结构包括在探针附近的内部通孔接触，并且电容器嵌入构成堆积层的树脂绝缘层中。

公开(公告)号：US06894396B2

公开(公告)日：2005-05-17

申请号：US10619483

申请日：2003-07-16

申请人： Takeshi Shioga ,  John David Baniecki ,  Kazuaki Kurihara ,  Yasuo Yamagishi

发明人： Takeshi Shioga ,  John David Baniecki ,  Kazuaki Kurihara ,  Yasuo Yamagishi

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/50 ,  H01L23/64 ,  H01L25/00 ,  H01L27/01 ,  H05K1/02 ,  H05K1/18 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L23/3107 ,  H01L23/642 ,  H01L24/48 ,  H01L24/81 ,  H01L27/016 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

摘要翻译： 半导体器件包括载体衬底，通过凸块安装在载体衬底上的集成电路芯片，以及用于稳定集成电路芯片在高频下的操作的电容器。 在半导体器件中，电容器电连接到集成电路芯片的底部的焊盘，并且电容器被设置为具有小于或等于载体衬底上的凸块的高度的载体衬底上的高度。

公开(公告)号：US20050179128A1

公开(公告)日：2005-08-18

申请号：US11104436

申请日：2005-04-13

申请人： Takeshi Shioga ,  John Baniecki ,  Kazuaki Kurihara ,  Yasuo Yamagishi

发明人： Takeshi Shioga ,  John Baniecki ,  Kazuaki Kurihara ,  Yasuo Yamagishi

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/50 ,  H01L23/64 ,  H01L25/00 ,  H01L27/01 ,  H05K1/02 ,  H05K1/18 ,  H01L23/34

CPC分类号： H01L23/50 ,  H01L23/3107 ,  H01L23/642 ,  H01L24/48 ,  H01L24/81 ,  H01L27/016 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/182 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.

公开(公告)号：US07557014B2

公开(公告)日：2009-07-07

申请号：US11600211

申请日：2006-11-16

申请人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

发明人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011

摘要： A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

摘要翻译： 一种半导体装置，包括：支撑基板，其具有填充有适于第一间距的导体的通孔; 形成在所述支撑基板上或上方的电容器; 形成在所述支撑基板上或上方的布线层，使一些所述通孔向上填充有通过所述电容器的导体，具有分支，并且具有不同于所述第一间距的第二间距的导线; 以及设置在所述布线层上或上方的多个半导体元件，具有适于所述第二间距的端子，并且经由所述端子与所述布线层连接。 其中具有窄端子间距的半导体元件，具有较宽节距的导线的支撑件和电容器的半导体装置被适当地电连接以实现具有减小的电感和大电容的去耦功能。

公开(公告)号：US20070065981A1

公开(公告)日：2007-03-22

申请号：US11600211

申请日：2006-11-16

申请人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

发明人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

IPC分类号： H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011

摘要： A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

公开(公告)号：US07176556B2

公开(公告)日：2007-02-13

申请号：US10092525

申请日：2002-03-08

申请人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

发明人： Keishiro Okamoto ,  Takeshi Shioga ,  Osamu Taniguchi ,  Koji Omote ,  Yoshihiko Imanaka ,  Yasuo Yamagishi

IPC分类号： H01L29/40 ,  H01L29/00 ,  H01L23/34

CPC分类号： H01L23/49816 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/3011

摘要： A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

摘要翻译： 一种半导体装置，包括：支撑基板，其具有填充有适于第一间距的导体的通孔; 形成在所述支撑基板上或上方的电容器; 形成在所述支撑基板上或上方的布线层，使一些所述通孔向上填充有通过所述电容器的导体，具有分支，并且具有不同于所述第一间距的第二间距的导线; 以及设置在所述布线层上或上方的多个半导体元件，具有适于所述第二间距的端子，并且经由所述端子与所述布线层连接。 其中具有窄端子间距的半导体元件，具有较宽节距的导线的支撑件和电容器的半导体装置被适当地电连接以实现具有减小的电感和大电容的去耦功能。

公开(公告)号：US07211899B2

公开(公告)日：2007-05-01

申请号：US10336728

申请日：2003-01-06

申请人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

发明人： Osamu Taniguchi ,  Yasuo Yamagishi ,  Koji Omote

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/15 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/0044 ,  H05K3/4605 ,  H05K2201/09827 ,  H05K2203/025

摘要： A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.

摘要翻译： 电路基板包括玻璃基板16，通过玻璃基板16形成的通孔18和埋在通孔18中的通孔电极20。 通孔18的开口宽度在玻璃基板的内部是最小的，并且朝向玻璃基板16的两个表面增加。 因此，可以防止通孔电极20的分离，而不会增加通孔内壁的表面粗糙度，并且可以减轻芯基板中产生的应力。

公开(公告)号：US06768205B2

公开(公告)日：2004-07-27

申请号：US10084923

申请日：2002-03-01

申请人： Osamu Taniguchi ,  Tomoko Miyashita ,  Yasuo Yamagishi ,  Koji Omote ,  Yoshihiko Imanaka

发明人： Osamu Taniguchi ,  Tomoko Miyashita ,  Yasuo Yamagishi ,  Koji Omote ,  Yoshihiko Imanaka

IPC分类号： H01L2713

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13009 ,  H01L2224/16 ,  H01L2224/73257 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011

摘要： The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.

摘要翻译： 本发明的目的是提供一种可靠的薄膜电路衬底或通孔形成的衬底，其以细间距设置有微通孔塞。 该目的通过在Si衬底上形成用作蚀刻阻挡层的绝缘层，然后使用半导体工艺在Si衬底中形成通孔，直到暴露出蚀刻阻挡层。 此外，在绝缘层上形成薄膜电路，并且在通孔处去除绝缘层，使薄膜电路露出。 根据需要，对薄膜电路进行热处理，然后用导电材料填充通孔，并形成鞋面电极。

公开(公告)号：US06580169B2

公开(公告)日：2003-06-17

申请号：US10191533

申请日：2002-07-10

申请人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

发明人： Seiki Sakuyama ,  Yasuo Yamagishi ,  Masataka Mizukoshi

IPC分类号： H01L2348

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1532 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0266 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0574 ,  H05K2203/0577 ,  H05K2203/0769

摘要： The present invention relates to a method for forming bumps on a substrate provided with electrode pads. The method includes providing a mask having openings corresponding to the electrode pads, filling each of the openings with a solder paste, and heat treating the solder paste, wherein the solder paste includes solder powder. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is greater than the thickness of the mask and no more than 1.5 times this thickness. Preferably, the solder powder contains no more than 10 wt % of particles whose diameter is not less than 40% the diameter of the opening portions, or no less than 30 wt % of particles whose diameter is 40 to 100% the thickness of the mask.

公开(公告)号：US06504966B2

公开(公告)日：2003-01-07

申请号：US10077342

申请日：2002-02-15

申请人： Masayuki Kato ,  Akio Sugama ,  Koji Tsukamoto ,  Masatoshi Ishii ,  Kishio Yokouchi ,  Yasuo Yamagishi ,  Motoyuki Nishizawa ,  Tsuyoshi Aoki

发明人： Masayuki Kato ,  Akio Sugama ,  Koji Tsukamoto ,  Masatoshi Ishii ,  Kishio Yokouchi ,  Yasuo Yamagishi ,  Motoyuki Nishizawa ,  Tsuyoshi Aoki

IPC分类号： G02B626

CPC分类号： G02F1/295 ,  G02B6/125 ,  G02B2006/12104 ,  G02B2006/12114 ,  G02B2006/12145 ,  G02F1/313

摘要： A prism pair is employed as an optical deflecting element. The prism pair is constructed by a slab waveguide, and first and second upper electrodes and first and second lower electrodes arranged on and under the slab waveguide. These electrodes are shaped into a wedge shape (e.g., triangular shape), and change the refractive index of a part of the slab waveguide by utilizing the electrooptic effect to change the propagation direction of light.

摘要翻译： 棱镜对被用作光学偏转元件。 棱镜对由平板波导构成，第一和第二上电极以及设置在平板波导上和下方的第一和第二下电极。 这些电极成形为楔形（例如，三角形），并且通过利用电光效应来改变平板波导的一部分的折射率以改变光的传播方向。