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    Debugging device and debugging method
    5.
    发明授权
    Debugging device and debugging method 有权
    调试器和调试方法

    公开(公告)号：US08370810B2

    公开(公告)日：2013-02-05

    申请号：US12273934

    申请日：2008-11-19

    申请人： Yuichi Oda

    发明人： Yuichi Oda

    IPC分类号： G06F9/44 ,  G06F11/00

    CPC分类号： G06F11/3644 ,  G06F11/3628

    摘要： A debugging device configured to debug a program includes an analysis section configured to analyze information of a code that does not need to be debugged in which a predetermined processing instruction is described, the code being generated by optimization of a compiler for a source code of the program, and an output section configured to output processing content information, a start address, and an end address of the code that does not need to be debugged which are obtained by the analysis.

    摘要翻译： 配置为调试程序的调试装置包括：分析部件，被配置为分析不需要调试的代码的信息，其中描述了预定处理指令，所述代码是通过优化编译器的源代码来生成的 程序和输出部分，被配置为输出通过分析获得的不需要调试的代码的处理内容信息，起始地址和结束地址。

    Information processing device
    6.
    发明授权
    Information processing device 有权
    信息处理装置

    公开(公告)号：US09042391B2

    公开(公告)日：2015-05-26

    申请号：US13611295

    申请日：2012-09-12

    申请人： Yuichi Oda

    发明人： Yuichi Oda

    IPC分类号： G06F12/14 ,  H04L29/08

    CPC分类号： G06F12/14 ,  G06F13/4022 ,  G06F2213/0038 ,  H04L29/08549

    摘要： According to one embodiment, an information processing device is provided with a memory, a plurality of processors, a router group, and an address protection unit. The plurality of the processors generate memory access packets each of which defines memory access requests for the memory, the memory access packet including an access destination address and an access type. The router group is provide with first routers which are connected to the memory and second routers which form transfer paths between the first router and the plurality of the processors, and transmits the memory access packets generated by the plurality of the processors to the memory. The address protection unit examines the memory access packets which pass through the first routers to detect a violated memory access.

    摘要翻译： 根据一个实施例，信息处理设备设置有存储器，多个处理器，路由器组和地址保护单元。 多个处理器产生存储器访问分组，每个存储器访问分组定义存储器的存储器访问请求，存储器访问分组包括访问目的地地址和访问类型。 路由器组提供连接到存储器的第一路由器和形成第一路由器和多个处理器之间的传输路径的第二路由器，并且将由多个处理器生成的存储器访问分组传送到存储器。 地址保护单元检查通过第一路由器的存储器访问分组以检测违反的存储器访问。

    IMAGE DISPLAY APPARATUS, IMAGE DISPLAY METHOD, AND IMAGE DISPLAY PROGRAM
    7.
    发明申请
    IMAGE DISPLAY APPARATUS, IMAGE DISPLAY METHOD, AND IMAGE DISPLAY PROGRAM 审中-公开
    图像显示装置，图像显示方法和图像显示程序

    公开(公告)号：US20120147045A1

    公开(公告)日：2012-06-14

    申请号：US13324044

    申请日：2011-12-13

    申请人： Hiroshi OIKE ,  Hiroaki Sakaguchi ,  Yuichi Oda ,  Tomoo Nakano ,  Yasushi Usami

    发明人： Hiroshi OIKE ,  Hiroaki Sakaguchi ,  Yuichi Oda ,  Tomoo Nakano ,  Yasushi Usami

    IPC分类号： G09G5/00

    CPC分类号： G06F3/04845 ,  G03B17/20 ,  G06F3/0483 ,  G06F3/04883

    摘要： An image display apparatus including a first storage means for storing at least one item of image data, correction condition data for correcting the image data, and corrected image data obtained after the image data is corrected on the basis of the correction condition data; an image processing means for producing the corrected image data; a display means comprising a screen for superimposing an original image based on the image data and a corrected image based on the corrected image data onto each other and displaying either the original image or the corrected image; an input means for selecting an image to be displayed on the display screen, and a display control means for switching between the images in response to an input from the input means, so that either the original image or the corrected image is displayed on the display screen.

    摘要翻译： 一种图像显示装置，包括：用于存储图像数据的至少一个项目的第一存储装置，用于校正图像数据的校正条件数据;以及基于校正条件数据校正图像数据之后获得的校正图像数据; 用于产生校正后的图像数据的图像处理装置; 显示装置，其包括用于基于图像数据叠加原始图像的屏幕和基于校正图像数据的校正图像彼此并显示原始图像或校正图像; 用于选择要在显示屏幕上显示的图像的输入装置，以及用于响应于来自输入装置的输入而在图像之间切换的显示控制装置，使得原始图像或校正图像被显示在显示器上 屏幕。

    System for debugging computer program
    8.
    发明授权
    System for debugging computer program 有权
    用于调试计算机程序的系统

    公开(公告)号：US08612942B2

    公开(公告)日：2013-12-17

    申请号：US12483675

    申请日：2009-06-12

    申请人： Yuichi Oda ,  Takashi Miura

    发明人： Yuichi Oda ,  Takashi Miura

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3648 ,  G06F12/0802

    摘要： First tag addresses and data are stored in association with first index addresses in a memory cell unit provided in a cache memory. The first tag addresses and the first index addresses are configured based on address information respectively. Designation address information is provided to designate an address to read one of the stored data. The designation address information is converted to a second index address and second tag address by an address converter, in order to read the one of the stored data according to the designation address information. The memory cell unit is accessed according to the obtained second index address. When one of the first tag addresses matches the second tag address, the one of the data corresponding to the one of the first tag addresses is read. The designation address information and the one of the data are displayed in a cache memory display unit.

    摘要翻译： 第一标签地址和数据与设置在高速缓冲存储器中的存储单元单元中的第一索引地址相关联地存储。 第一标签地址和第一索引地址分别基于地址信息配置。 提供指定地址信息以指定地址以读取所存储的数据之一。 通过地址转换器将指定地址信息转换为第二索引地址和第二标签地址，以便根据指定地址信息读取存储的数据之一。 根据所获得的第二索引地址访问存储单元单元。 当第一标签地址之一与第二标签地址匹配时，读取与第一标签地址之一相对应的数据之一。 指定地址信息和数据中的一个显示在高速缓冲存储器显示单元中。

    REACTION APPARATUS, AND REACTION METHOD
    9.
    发明申请
    REACTION APPARATUS, AND REACTION METHOD 审中-公开
    反应装置和反应方法

    公开(公告)号：US20100022771A1

    公开(公告)日：2010-01-28

    申请号：US12441674

    申请日：2007-09-14

    申请人： Noriyuki Yoneda ,  Yuichi Oda ,  Yasuo Nakanishi

    发明人： Noriyuki Yoneda ,  Yuichi Oda ,  Yasuo Nakanishi

    IPC分类号： C07D487/02 ,  B01J19/00 ,  C07C55/06

    CPC分类号： C07D487/04 ,  B01J19/243 ,  B01J2219/00063 ,  C07C67/343 ,  C07C69/716

    摘要： The present invention is directed at obtaining a high yield of a target substance and simultaneously securing high productivity.A reaction apparatus 10 has: a main flow channel 12 having an inner diameter of 3 mm, in which a raw material M1 flows; an introduction flow channel 14 in which a raw material M2 that causes a chemical reaction with the raw material M1 flows; and five branch introduction flow channels 16a to 16e which are branched from the introduction flow channel 14 and introduce the raw material M2 to the main flow channel 12, at predetermined introduction points 12o to 12s in the main flow channel 12. Here, in the main flow channel 12, the flow channel lengths of the flow channels 12b to 12d between adjacent introduction points 12p to 12s are not longer than those of the flow channels 12a to 12c between the next previous adjacent introduction points 12o to 12r in a flow direction of the raw material M1. At least one length of the flow channels 12b to 12d between the adjacent introduction points 12p to 12s is shorter than lengths of the flow channels 12a to 12c between previous adjacent introduction points 12o to 12r in the flow direction of the raw material M1.

    摘要翻译： 本发明涉及获得高产率的目标物质并同时确保高生产率。 反应装置10具有：原料M1流过的内径为3mm的主流路12; 导入与原料M1发生化学反应的原料M2的导入流路14; 以及从导入流路14分支并将原料M2引入主流路12的五个分支导入流路16a〜16e，在主流路12中的预定的导入点12o〜12s。这里，主 在流路12中，相邻导入点12p〜12s之间的流路12b〜12d的流路长度不比前一相邻导入点12o〜12r之间的流路12a〜12c的流路长度在 原料M1。 在相邻的导入点12p〜12s之间的流路12b〜12d的至少一个长度比原料M1的流动方向的前一相邻导入点12o〜12r之间的流路12a〜12c的长度短。