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    Semiconductor integrated circuit device having a sampling signal generation circuit
    3.
    发明授权
    Semiconductor integrated circuit device having a sampling signal generation circuit 有权
    具有采样信号发生电路的半导体集成电路装置

    公开(公告)号：US06954096B2

    公开(公告)日：2005-10-11

    申请号：US10760489

    申请日：2004-01-21

    Applicant: Kenji Ito ,  Takuya Harada ,  Hirofumi Isomura

    Inventor： Kenji Ito ,  Takuya Harada ,  Hirofumi Isomura

    IPC: H02P7/29 ,  H03K3/017 ,  H03K5/00 ,  H03K5/06 ,  H03K19/003 ,  H03M1/08

    CPC classification number: H02M7/48 ,  H02M2001/0012 ,  H02P7/29

    Abstract: A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when “delay time td+allowance time ta” has elapsed from a start signal Sp. The delay time td is shorter than “the minimum time width of H level of PWM signal SPWM1−allowance time ta”. The delay time td is also time from the variation of level of the PWM signal SPWM1 to actual variation in the passage of current through a power section.

    Abstract translation: 提供了一种半导体集成电路器件，以减少在PWM驱动部分中产生的PWM噪声对IC中的模拟电压处理部分的不利影响，其中数字和模拟电路组合在单个芯片上。 当从起始信号Sp经过“延迟时间td +容许时间ta”的预定时间时，采样信号产生电路将采样信号St输出到A / D转换器。 延迟时间td短于“PWM信号SPWM 1的容许时间ta”的H电平的最小时间宽度。 延迟时间td也是从PWM信号SPWM 1的电平变化到通过功率部分的电流通过的实际变化的时间。

    Memory control apparatus for serial memory
    4.
    发明授权
    Memory control apparatus for serial memory 失效
    用于串行存储器的存储器控​​制装置

    公开(公告)号：US06798707B2

    公开(公告)日：2004-09-28

    申请号：US10234132

    申请日：2002-09-05

    Applicant: Akimasa Niwa ,  Takuya Harada ,  Takayuki Aono ,  Shuji Agatsuma

    Inventor： Akimasa Niwa ,  Takuya Harada ,  Takayuki Aono ,  Shuji Agatsuma

    IPC: G11C700

    CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C16/32 ,  G11C2207/107 ,  G11C2216/30

    Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

    Abstract translation: 用于控制串行存储器中的存储器阵列的操作的存储器控​​制装置使用命令控制部分，用于将作为外部提供的串行数据集合接收的指令的位与一个时钟的相应的一系列周期相结合 信号，其中每组串行数据被格式化为在起始位之前的命令数据部分，由此检测起始位到移位寄存器的MSB级的移位，并用于终止向移位寄存器提供时钟信号， 从而消除了使用计数器电路。 检测到起始位移位到移位寄存器的MSB级之后的任何额外的时钟信号周期，从而可以可靠地消除接收到的时钟信号中由噪声引起的操作错误。

    NC data management apparatus and method
    7.
    发明授权
    NC data management apparatus and method 失效
    NC数据管理装置及方法

    公开(公告)号：US07142936B2

    公开(公告)日：2006-11-28

    申请号：US10805002

    申请日：2004-03-19

    Applicant: Masashi Yokomori ,  Keiji Hanada ,  Kouichi Kanematsu ,  Takuya Harada

    Inventor： Masashi Yokomori ,  Keiji Hanada ,  Kouichi Kanematsu ,  Takuya Harada

    IPC: G06F19/00 ,  G06F7/00

    CPC classification number: G05B19/41865 ,  G05B19/41875 ,  G05B2219/32129 ,  G05B2219/32187 ,  G05B2219/32238 ,  Y02P90/18 ,  Y02P90/185 ,  Y02P90/20 ,  Y02P90/22

    Abstract: A production system including a production line having a series of pieces of production equipment each of which has a parts supply unit. The production system includes: an NC management apparatus that is connected with each piece of the production equipment via a local-area network and acquires therefrom NC data used for operating each piece of the production equipment; and a scheduling apparatus that generates a production schedule and transmits the generated production schedule to the NC management apparatus via the local-area network. Here, the NC management apparatus generates, for each piece of the production equipment, data that is required to perform production according to the production schedule, obtains, for each piece of the production equipment, values that represent differences between current NC data that has been most recently acciuired and the generated data, and outputs the values.

    Abstract translation: 一种生产系统，包括具有一系列生产设备的生产线，每个生产设备具有部件供应单元。 生产系统包括：NC管理装置，通过局域网连接每个生产设备，并从中获取用于操作每个生产设备的NC数据; 以及调度装置，其经由所述局域网生成生产调度并将所生成的生产调度发送到所述NC管理装置。 这里，NC管理装置对于每个生产设备生成根据生产计划进行生产所需的数据，对于每个生产设备，获得表示当前NC数据之间的差异的值 最近收到的和生成的数据，并输出值。

    A/D conversion device having input level shift and output correction function
    8.
    发明申请
    A/D conversion device having input level shift and output correction function 失效
    具有输入电平移位和输出校正功能的A / D转换装置

    公开(公告)号：US20050168363A1

    公开(公告)日：2005-08-04

    申请号：US11043192

    申请日：2005-01-27

    Applicant: Takuya Harada

    Inventor： Takuya Harada

    IPC: H03M1/12 ,  H03M1/06 ,  H03M1/18 ,  H03M1/34

    CPC classification number: H03M1/181

    Abstract: In an A/D conversion device, one level shift circuit shifts an input voltage to the low potential side by Vt1, and another level shift circuit shifts the input voltage to the high potential side by Vt2. A multiplexer selects either of the shifted voltages to an A/D converter. In a correction mode, a correction data holding circuit holds values of reference voltages that are also A/D converted after being passed through the one level shift circuit and values of reference voltages that are A/D converted by being passed through the other level shift circuit, as correction values. A correction control circuit corrects the A/D converted value using the correction values.

    Abstract translation: 在A / D转换装置中，一个电平移位电路将输入电压移动到低电位侧Vt 1，另一个电平移位电路将输入电压移动到高电位侧Vt 2。 多路复用器选择移位电压中的任一个到A / D转换器。 在校正模式中，校正数据保持电路保持在通过一电平移位电路之后也进行A / D转换的参考电压的值和通过其他电平移位进行A / D转换的参考电压的值 电路，作为校正值。 校正控制电路使用校正值校正A / D转换值。

    Offset voltage correction circuit
    9.
    发明授权
    Offset voltage correction circuit 失效
    偏移电压校正电路

    公开(公告)号：US6054887A

    公开(公告)日：2000-04-25

    申请号：US112284

    申请日：1998-07-09

    Applicant: Masakiyo Horie ,  Takuya Harada

    Inventor： Masakiyo Horie ,  Takuya Harada

    IPC: H03F3/34 ,  H03F1/30 ,  H03L5/00

    CPC classification number: H03F1/304

    Abstract: An offset voltage correction circuit for an operational amplifier (1) includes an offset voltage varying device (16, 17, 20, 21-23) for varying an offset voltage in the operational amplifier (1) in response to an offset voltage control value. A comparing device (25) operates for comparing an output voltage from the operational amplifier (1) with a prescribed reference voltage. A control device (19, 300) operates for outputting the offset voltage control value to the offset voltage varying device, for changing the offset voltage control value, for storing, in response to a result of the comparing by the comparing device (25), a digital signal representative of the offset voltage control value at which the output voltage from the operational amplifier (1) and the prescribed reference voltage are equal, and for correcting the offset voltage in the operational amplifier (1) in response to the stored digital signal.

    Abstract translation: 用于运算放大器（1）的偏移电压校正电路包括用于响应于偏移电压控制值改变运算放大器（1）中的偏移电压的偏移电压变化器件（16,17,20,21-23）。 比较装置（25）用于将来自运算放大器（1）的输出电压与规定的参考电压进行比较。 控制装置（19,300）用于将偏移电压控制值输出到偏移电压变化装置，用于改变偏移电压控制值，用于响应于比较装置（25）的比较结果存储， 表示来自运算放大器（1）和规定参考电压的输出电压相等的偏移电压控制值的数字信号，并且用于响应于所存储的数字信号来校正运算放大器（1）中的偏移电压 。

    Valuable threshold waveform shaping apparatus
    10.
    发明授权
    Valuable threshold waveform shaping apparatus 失效
    宝贵的阈值波形整形装置

    公开(公告)号：US5841301A

    公开(公告)日：1998-11-24

    申请号：US618620

    申请日：1996-03-20

    Applicant: Masakiyo Horie ,  Takuya Harada

    Inventor： Masakiyo Horie ,  Takuya Harada

    IPC: G01D5/245 ,  G01D5/244 ,  G01R23/06 ,  H03K5/08 ,  H03K5/01

    CPC classification number: H03K5/086

    Abstract: A waveform shaping apparatus includes a comparing device for comparing a sensor output signal with a threshold voltage to convert the sensor output signal into a waveform shaped signal. The comparing device outputs the waveform shaped signal. The waveform shaping apparatus also includes a frequency-to-voltage converting device for generating the threshold voltage in response to a frequency of the output signal from the comparing device. In the frequency-to-voltage converting device, a clock signal is generated in response to the output signal from the comparing device. The clock signal has a period proportional to a period of the output signal from the comparing device. A counting device is operative for counting pulses in the clock signal generated by the clock signal generating device for every given period, and outputting a signal representing a counted pulse number depending on the frequency of the output signal from the comparing device. A D/A converting device is operative for converting the output signal from the counting device into a voltage signal which depends on the counted pulse number. The threshold voltage is generated in response to the voltage signal generated by the D/A converting device.

    Abstract translation: 波形整形装置包括比较装置，用于将传感器输出信号与阈值电压进行比较，以将传感器输出信号转换为波形形状信号。 比较装置输出波形整形信号。 波形整形装置还包括频率 - 电压转换装置，用于响应于来自比较装置的输出信号的频率产生阈值电压。 在频率 - 电压转换装置中，响应于来自比较装置的输出信号产生时钟信号。 时钟信号具有与比较装置的输出信号的周期成比例的周期。 计数装置用于对每个给定时间段由时钟信号产生装置产生的时钟信号中的脉冲进行计数，并根据来自比较装置的输出信号的频率输出表示计数脉冲数的信号。 D / A转换装置用于将来自计数装置的输出信号转换成取决于计数的脉冲数的电压信号。 响应于由D / A转换器产生的电压信号产生阈值电压。

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