公开(公告)号：US06359335B1

公开(公告)日：2002-03-19

申请号：US09711036

申请日：2000-11-13

申请人： Thomas H. Distefano ,  John W. Smith ,  Craig Mitchell

发明人： Thomas H. Distefano ,  John W. Smith ,  Craig Mitchell

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/11003 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip packaging assembly comprising a frame having a central aperture, a flexible substrate attached to the frame across the central aperture, and a unitary support structure having a plurality of apertures therethrough attached to the substrate within the central aperture of the frame with at least some of the substrate terminals underlying the unitary support structure. A chip is disposed within each aperture and attached to the substrate with the electrical contacts of the chip connected to the substrate terminals. A compliant layer is disposed between the substrate and the unitary support structure and between the substrate and the chip.

公开(公告)号：US5659952A

公开(公告)日：1997-08-26

申请号：US365699

申请日：1994-12-29

申请人： Zlata Kovac ,  Craig Mitchell ,  Thomas H. Distefano ,  John W. Smith

发明人： Zlata Kovac ,  Craig Mitchell ,  Thomas H. Distefano ,  John W. Smith

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H05K3/40 ,  H05K3/34

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H05K3/4084 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  H05K3/361 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174

摘要： A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The compliant interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

摘要翻译： 一种用于在半导体芯片和其支撑衬底之间提供平面和兼容接口以适应其间的热膨胀失配的方法和装置。 兼容接口包括限定相邻焊盘之间的通道的多个柔性焊盘。 垫通常在柔性膜芯片载体和芯片之间被压缩。 在通道内进一步布置柔顺填料以形成具有受控厚度的均匀包封层。

公开(公告)号：US5929517A

公开(公告)日：1999-07-27

申请号：US365749

申请日：1994-12-29

申请人： Thomas H. Distefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

发明人： Thomas H. Distefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H05K13/04

CPC分类号： H01L24/50 ,  H01L21/565 ,  H01L23/3121 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T29/49146

摘要： Semiconductor chip packages and methods of fabricating the same. The package includes a thermally conductive protective structure having an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure. A chip is disposed in the indentation so that the front surface of the chip, with contacts thereon, faces toward the front of the structure. A flexible dielectric film having terminals thereon is placed on the flange surface, and a compliant material is disposed between the film and the flange surface. The terminals on the film are connected to the contacts on the chip. The individual terminals on the film are movable with respect to the protective structure, which facilitates mounting and compensation for thermal expansion.

摘要翻译： 半导体芯片封装及其制造方法。 该封装包括导热保护结构，其具有向前侧开口的凹口和至少部分地围绕凹口并面向结构前部的凸缘表面。 芯片设置在凹陷中，使得具有触点的芯片的前表面朝向结构的前部。 其上具有端子的柔性电介质膜放置在凸缘表面上，并且柔性材料设置在膜和凸缘表面之间。 胶片上的端子连接到芯片上的触点。 胶片上的各个端子相对于保护结构是可移动的，这有助于热膨胀的安装和补偿。

公开(公告)号：US06897090B2

公开(公告)日：2005-05-24

申请号：US10430986

申请日：2003-05-07

申请人： Thomas H. DiStefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

发明人： Thomas H. DiStefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L21/44

CPC分类号： H01L24/50 ,  H01L21/565 ,  H01L23/3121 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2924/00012

摘要： A component incorporating a dielectric element such as a polymeric film with leads and terminals thereon is assembled with a semiconductor chip and bond regions of the leads are connected to contacts of the chip. At least one lead incorporates a plural set of connecting regions connecting the bond region of that lead to a plurality of terminals. One or more of the connecting regions in each such plural set are severed so as to leave less than all of the terminals associated with each such plural set connected to the contacts of the chip.

摘要翻译： 将包含诸如其上具有引线和端子的聚合物膜的电介质元件的部件与半导体芯片组装，并且引线的接合区域连接到芯片的触点。 至少一个引线包括将该引线的键合区域连接到多个端子的多组连接区域。 每个这样的多个组中的一个或多个连接区域被切断，以便留下少于与连接到芯片的触点的每个这样的多个组相关联的所有终端。

公开(公告)号：US6133639A

公开(公告)日：2000-10-17

申请号：US842313

申请日：1997-04-24

申请人： Zlata Kovac ,  Craig Mitchell ,  Thomas H. Distefano ,  John W. Smith

发明人： Zlata Kovac ,  Craig Mitchell ,  Thomas H. Distefano ,  John W. Smith

IPC分类号： H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/36 ,  H05K3/40 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/72 ,  H01L24/75 ,  H05K3/4084 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81801 ,  H01L2224/83136 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/118 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  H05K3/361 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49174

摘要： A method and an apparatus for providing a planar and compliant interface between a semiconductor chip and its supporting substrate to accommodate for the thermal coefficient of expansion mismatch therebetween. The complaint interface is comprised of a plurality of compliant pads defining channels between adjacent pads. The pads are typically compressed between a flexible film chip carrier and the chip. A compliant filler is further disposed within the channels to form a uniform encapsulation layer having a controlled thickness.

摘要翻译： 一种用于在半导体芯片和其支撑衬底之间提供平面和兼容接口以适应其间的热膨胀失配的方法和装置。 投诉界面由在相邻的焊盘之间限定通道的多个柔性焊盘构成。 垫通常在柔性膜芯片载体和芯片之间被压缩。 在通道内进一步布置柔顺填料以形成具有受控厚度的均匀包封层。

公开(公告)号：US06603209B1

公开(公告)日：2003-08-05

申请号：US09306623

申请日：1999-05-06

申请人： Thomas H. DiStefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

发明人： Thomas H. DiStefano ,  Konstantine Karavakis ,  Craig Mitchell ,  John W. Smith

IPC分类号： H01L2348

CPC分类号： H01L24/50 ,  H01L21/565 ,  H01L23/3121 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention provides a method for fabricating a compliant microelectronic device package and an associated apparatus for substantially obviating thermal, compliancy and interconnection problems. Flexible, dielectric layers are used having on a first surface a plurality conductive leads which are each electrically coupled at a first end to at least one conductive pad also coupled to the first surface of the dielectric layers. A second end of the conductive leads are further coupled between the dielectric layers across a bonding gap. A compliant layer is then coupled to the bottom surface of the dielectric layers. One of the dielectric layers is coupled to the surface of a die by one of the compliant layer such that the die bond pads are juxtaposed with respective leads in the bonding gap. This assembly is attached to a protective structure and is encapsulated. A solder mask may be placed over the exposed surface of the dielectric layers to cover the leads and prevent shoring. Further, a conductive layer may be used in the package as a ground layer of a voltage reference layer.

摘要翻译： 本发明提供一种用于制造柔性微电子器件封装的方法和用于基本上消除热，并联和互连问题的相关装置。 使用柔性介电层，其在第一表面上具有多个导电引线，多个导电引线在第一端处电耦合到还耦合到电介质层的第一表面的至少一个导电焊盘。 导电引线的第二端进一步通过结合间隙耦合在介电层之间。 然后将柔顺层耦合到电介质层的底表面。 一个电介质层通过柔性层之一耦合到管芯的表面，使得管芯接合焊盘与接合间隙中的各个引线并置。 该组件附接到保护结构并被封装。 可以将焊接掩模放置在电介质层的暴露表面上以覆盖引线并防止支撑。 此外，可以在封装中使用导电层作为电压参考层的接地层。

公开(公告)号：US06232152B1

公开(公告)日：2001-05-15

申请号：US09067310

申请日：1998-04-28

申请人： Thomas H. DiStefano ,  John W. Smith ,  Craig Mitchell

发明人： Thomas H. DiStefano ,  John W. Smith ,  Craig Mitchell

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/50 ,  H01L24/97 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05599 ,  H01L2224/11003 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/86 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A method of manufacturing a plurality of semiconductor chips packages and the resulting chip package assemblies. The method includes providing a circuitized substrate having terminals and leads. A spacer layer is deposited or attached to the substrate and each chip is then attached to the spacer layer. The leads interconnect contacts on the chip to the terminals on the substrate wherein at least some of the terminals lie outside the periphery of the chip. Typically, the spacer layer is comprised of a compliant or resilient material. A curable encapsulant material is deposited so as to encapsulate the leads and at least one surface of the chip. A unitary support structure is then aligned and attached to the encapsulant around the edges of the chips. The encapsulant material is then cured thereby defining a composite of chip assemblies which may be singulated into individual chip packages.

摘要翻译： 一种制造多个半导体芯片封装的方法和所得到的芯片封装组件。 该方法包括提供具有端子和引线的电路化基板。 将间隔层沉积或附着到基底上，然后将每个芯片附接到间隔层。 引线将芯片上的接触件连接到衬底上的端子，其中至少一些端子位于芯片的外围。 通常，间隔层由顺应性或弹性材料构成。 沉积可固化的密封剂材料以便封装引线和芯片的至少一个表面。 然后将整体支撑结构对准并附接到围绕芯片边缘的密封剂。 密封剂材料然后被固化，从而限定了可以被分成单个芯片封装的芯片组件的复合材料。

公开(公告)号：US5663106A

公开(公告)日：1997-09-02

申请号：US246113

申请日：1994-05-19

申请人： Konstantine Karavakis ,  Thomas H. Distefano ,  John W. Smith, Jr. ,  Craig Mitchell

发明人： Konstantine Karavakis ,  Thomas H. Distefano ,  John W. Smith, Jr. ,  Craig Mitchell

IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/24 ,  H01L23/31 ,  H01L21/60

CPC分类号： H01L21/568 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/3114 ,  H01L24/97 ,  H01L2224/11003 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/3025 ,  Y10T29/49146

摘要： A method of packaging a semiconductor chip assembly includes the encapsulation of the same after establishing an encapsulation area and providing a physical barrier for protecting the terminals of a chip carrier. An alternative or supplement to providing a physical barrier is to provide a preform of an encapsulation material which includes a predetermined volume of such material so that only the encapsulation area is filled. For a semiconductor chip assembly which does not yet have an elastomeric layer, a method of simultaneously forming such an elastomeric layer and encapsulating a semiconductor chip assembly is also provided.

摘要翻译： 封装半导体芯片组件的方法包括在建立封装区域之后对其进行封装，并提供用于保护芯片载体的端子的物理屏障。 提供物理屏障的替代或补充是提供包含材料的预成型件，其包括预定体积的这种材料，使得仅填充封装区域。 对于还没有弹性体层的半导体芯片组件，还提供了同时形成这种弹性体层并封装半导体芯片组件的方法。

公开(公告)号：US06202299B1

公开(公告)日：2001-03-20

申请号：US09209216

申请日：1998-12-11

申请人： Thomas H. DiStefano ,  Gus Karavakis ,  Zlata Kovac ,  Craig Mitchell

发明人： Thomas H. DiStefano ,  Gus Karavakis ,  Zlata Kovac ,  Craig Mitchell

IPC分类号： H05K334

CPC分类号： H01L24/86 ,  H01L21/4821 ,  H01L21/6835 ,  H01L23/495 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49171 ,  H01L2924/00

摘要： A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.

摘要翻译： 半导体芯片连接部件在其底表面上设置有粘合剂，期望地为固体，非粘性状态。 粘合剂可以以覆盖小于所有组分底部表面的图案存在，以便当粘合剂将组分粘合到芯片的顶表面时提供无空隙的界面。 粘合剂期望地通过从芯片本身传递的热量而变成可流动状态。 连接部件可以包括在顶表面下方的迹线区域中具有基底金属条的引线和突出超过顶层边缘的贵金属部分。 可流动的可固化材料封装基体金属部分。 因为贱金属部分理想地没有底切部分，所以在形成部件期间可以以无空隙的方式将其包封。

公开(公告)号：US6045655A

公开(公告)日：2000-04-04

申请号：US170906

申请日：1998-10-13

申请人： Thomas H. DiStefano ,  Gus Karavakis ,  Zlata Kovac ,  Craig Mitchell

发明人： Thomas H. DiStefano ,  Gus Karavakis ,  Zlata Kovac ,  Craig Mitchell

IPC分类号： H01L21/48 ,  H01L21/58 ,  H01L21/60 ,  H01L21/68 ,  H01L23/495 ,  H01L23/498 ,  H05K1/14

CPC分类号： H01L24/86 ,  H01L21/4821 ,  H01L21/6835 ,  H01L23/495 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49171

摘要： A semiconductor chip connection component is provided with an adhesive, desirably in a solid, non-tacky condition on its bottom surface. The adhesive may be present in a pattern covering less than all of the component bottom surface, so as to provide a void-free interface when the adhesive bonds the component to the top surface of a chip. The adhesive desirably is brought to a flowable condition by heat transferred from the chip itself. The connection component may include leads having base metal strips in a trace area underlying the top surface and noble metal portions protruding beyond an edge of the top layer. A flowable, curable material encapsulates the base metal sections. Because the base metal sections desirably are free of undercuts, the same can be encapsulated in a void-free manner during formation of the component.

摘要翻译： 半导体芯片连接部件在其底表面上设置有粘合剂，期望地为固体，非粘性状态。 粘合剂可以以覆盖小于所有组分底部表面的图案存在，以便当粘合剂将组分粘合到芯片的顶表面时提供无空隙的界面。 粘合剂期望地通过从芯片本身传递的热量而变成可流动状态。 连接部件可以包括在顶表面下方的迹线区域中具有基底金属条的引线和突出超过顶层边缘的贵金属部分。 可流动的可固化材料封装基体金属部分。 因为贱金属部分理想地没有底切部分，所以在形成部件期间可以以无空隙的方式将其包封。