利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

142 条记录 (耗时 0.034 秒)

    Coding transmission equipment for carrying out coding with adaptive quantization
    1.
    发明授权
    Coding transmission equipment for carrying out coding with adaptive quantization 失效
    编码用自适应量化进行编码的传输设备

    公开(公告)号：US4831636A

    公开(公告)日：1989-05-16

    申请号：US134818

    申请日：1987-12-18

    申请人： Tomohiko Taniguchi ,  Kohei Iseda ,  Yoshihiro Tomita ,  Fumio Amano ,  Shigeyuki Unagami ,  Shoji Tominaga

    发明人： Tomohiko Taniguchi ,  Kohei Iseda ,  Yoshihiro Tomita ,  Fumio Amano ,  Shigeyuki Unagami ,  Shoji Tominaga

    IPC分类号： G06T9/00 ,  H04B14/04 ,  H04B14/06

    CPC分类号： H04B14/046 ,  G06T9/005 ,  H04B14/068

    摘要： Coding transmission equipment wherein an plurality of adaptive coding units having different processing characteristics are provided, and the adaptive coding unit having the optimum processing characteristic for a current input signal is selected from among the plurality of adaptive coding units, and an output signal from the optimum adaptive coding unit and the unit number thereof are transmitted to the receiver side. At the receiver side, the processing characteristic of a decoder is changed to become the optimum processing characteristic indicated by the received unit number, whereby a high quality recovered signal is realized.

    摘要翻译： 编码传输设备，其中提供具有不同处理特性的多个自适应编码单元，并且从多个自适应编码单元中选择具有用于当前输入信号的最佳处理特性的自适应编码单元，以及来自最佳 自适应编码单元及其单元号被发送到接收机侧。 在接收机侧，将解码器的处理特性改变为由接收到的单元号表示的最佳处理特性，从而实现高质量的恢复信号。

    Variable rate coder
    2.
    发明授权
    Variable rate coder 失效
    可变速率编码器

    公开(公告)号：US5159611A

    公开(公告)日：1992-10-27

    申请号：US860210

    申请日：1992-03-27

    申请人： Yoshihiro Tomita ,  Kohei Iseda ,  Shigeyuki Unagami

    发明人： Yoshihiro Tomita ,  Kohei Iseda ,  Shigeyuki Unagami

    IPC分类号： G06T9/00 ,  H04B14/04

    CPC分类号： H04B14/046 ,  H04N19/154 ,  H04N19/30 ,  H04N19/60

    摘要： A variable rate coder for transforming an input signal into a low bit rate digital signal, comprising: a plurality of coding units each comprising an output quantizer having a different number of output bits, and each independently transforming the input signal into a respective compressed digital signal. A plurality of bit rate determined circuits are provided to determine an output of one of the plurality of coding units as a candidate output of the coder by a respective individual determining method, in which method, the quality of the signal which is regenerated from the output of each coding unit is compared with an individual predetermined quality evaluating standard, and then the candidate output of the coding unit having the smallest number of output bits, among the candidate outputs of coding units satisfying each standard, is determined as the actual output of the coder. One candidate output, among the plurality of the determined candidate outputs and, which is further determined by a most suitable determining method relative to the level of the input signal, thus is selected as the actual output of the coder. Further, when the number of the output bits in each of the coding units can be variably set, the most suitable number of output bits for the actual output of the coder is calculated based on prediction gains of the coding units, a required signal-to-noise ratio of the coder, and an ADC signal-to-noise ratio at the analog to digital converter, and the number of the output bits in each of the coding units is set based on the above calculated value, before the above operation by the bit rate determining circuits.

    摘要翻译： 一种用于将输入信号变换为低比特率数字信号的可变速率编码器，包括：多个编码单元，每个编码单元包括具有不同数目的输出位的输出量化器，并且各自独立地将输入信号变换为相应的压缩数字信号 。 提供多个比特率确定电路，以通过各自的确定方法确定多个编码单元之一的输出作为编码器的候选输出，在该方法中，从输出再生的信号的质量 将每个编码单元与各个预定质量评估标准进行比较，然后确定满足每个标准的编码单元的候选输出中具有最小输出比特数的编码单元的候选输出作为实际输出 编码器 因此，选择多个确定的候选输出中的一个候选输出，并且相对于输入信号的电平进一步由最合适的确定方法确定，作为编码器的实际输出。 此外，当可以可变地设置每个编码单元中的输出比特数时，基于编码单元的预测增益来计算编码器的实际输出的最合适数量的输出比特，所需信号到 编码器的噪声比和模数转换器的ADC信噪比，并且在上述操作之前，基于上述计算值设置每个编码单元中的输出比特数， 比特率确定电路。

    Methods for making multi-chip packaging using an interposer
    7.
    发明授权
    Methods for making multi-chip packaging using an interposer 有权
    使用插入片进行多芯片封装的方法

    公开(公告)号：US08387240B2

    公开(公告)日：2013-03-05

    申请号：US12955816

    申请日：2010-11-29

    申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

    IPC分类号： H01K3/10

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

    摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

    摘要翻译： 在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。 电绝缘层形成在主体的侧壁和上表面上。 在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的 间距比第一金属垫。 在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。 身体通过下表面变薄，并且通孔中的电绝缘层被暴露。 在变薄之后，去除通孔中的电绝缘层的一部分。 主体耦合到基板。