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公开(公告)号：US07501345B1
公开(公告)日：2009-03-10
申请号：US12057688
申请日：2008-03-28
申请人： Veeraraghaven S. Basker , Hariklia Deligianni , Balasubramanian S. Pranatharthi Haran , James J. Kelly , Christian Lavoie , George G. Totir
发明人： Veeraraghaven S. Basker , Hariklia Deligianni , Balasubramanian S. Pranatharthi Haran , James J. Kelly , Christian Lavoie , George G. Totir
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , C23C18/1642 , C23C18/54 , H01L21/288
摘要： Silicide formation processes are disclosed that use an electrochemical displacement reaction in the absence of an externally applied current or potential. In an embodiment, a method for forming an integrated circuit comprises: depositing a metallic material upon select areas of a semiconductor topography comprising silicon by contacting the semiconductor topography with an aqueous solution comprising an acid and a metal salt to cause an electrochemical displacement reaction in the absence of an externally applied current or potential, wherein a concentration of the metal salt in the aqueous solution is about 0.01 millimolar to about 0.5 millimolar; and annealing the metallic material to form a silicide upon the areas of the semiconductor topography comprising the silicon.
摘要翻译： 公开了在没有外部施加的电流或电位的情况下使用电化学置换反应的硅化物形成方法。 在一个实施例中，一种用于形成集成电路的方法包括：通过使半导体形貌与包含酸和金属盐的水溶液接触，在包含硅的半导体形貌的选择区域上沉积金属材料，以引起电化学位移反应 不存在外部施加的电流或电势，其中金属盐在水溶液中的浓度为约0.01毫摩尔至约0.5毫摩尔; 并且在包括硅的半导体形貌的区域上退火金属材料以形成硅化物。
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2.发明申请METHODS FOR FABRICATING SILICON CARRIERS WITH CONDUCTIVE THROUGH-VIAS WITH LOW STRESS AND LOW DEFECT DENSITY 有权具有低应力和低缺陷密度的导电通孔的硅载体的制备方法公开(公告)号：US20080164573A1
公开(公告)日：2008-07-10
申请号：US11620423
申请日：2007-01-05
申请人： Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
发明人： Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/433 , H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/055 , H01L23/481 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/16195 , H01L2924/3025 , H01L2924/00
摘要： Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
摘要翻译： 提供了用于制造具有导电通孔的硅载体的方法，其允许以低缺陷密度高产量制造硅载体。 特别地，提供了能够制造硅的方法，具有通孔直径，例如直径为1至10微米，垂直厚度小于10微米至大于300微米，这对于生产过程中的热机械应力是坚固的 以显着地最小化硅，绝缘体，衬里和导体材料之间的通孔侧壁界面处的热机械运动。
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3.发明授权Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density 有权用于制造具有低应力和低缺陷密度的导电通孔的硅载体的方法公开(公告)号：US07863189B2
公开(公告)日：2011-01-04
申请号：US11620423
申请日：2007-01-05
申请人： Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
发明人： Veeraraghaven S. Basker , John Michael Cotte , Hariklia Deligianni , John Ulrich Knickerbocker , Keith T. Kwietniak
IPC分类号： H01L21/44
CPC分类号： H01L23/433 , H01L21/486 , H01L21/6835 , H01L21/76898 , H01L23/055 , H01L23/481 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/16195 , H01L2924/3025 , H01L2924/00
摘要： Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.
摘要翻译： 提供了用于制造具有导电通孔的硅载体的方法，其允许高产量制造具有低缺陷密度的硅载体。 特别地，提供了这样的方法，其能够制造具有通孔直径的硅载体，其直径为小于10微米至大于300微米的垂直厚度，其垂直厚度小于10微米至大于300微米，这对于在生产期间的热机械应力是坚固的 显着地最小化硅，绝缘体，衬里和导体材料之间的通孔侧壁界面处的热机械运动。
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4.发明申请VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC 审中-公开垂直型材FinFET通过薄型电介质形成的FinFET栅极公开(公告)号：US20090321833A1
公开(公告)日：2009-12-31
申请号：US12145616
申请日：2008-06-25
申请人： Veeraraghaven S. Basker , Hariklia Deligianni , Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Veeraraghaven S. Basker , Hariklia Deligianni , Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods of making vertical profile FinFET gate electrodes via plating upon a thin gate dielectric are disclosed. In one embodiment, a method for forming a transistor, comprises: providing a semiconductor topography comprising a semiconductor substrate and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.
摘要翻译： 公开了通过在薄栅极电介质上电镀制造垂直轮廓FinFET栅电极的方法。 在一个实施例中，一种用于形成晶体管的方法包括：提供包括半导体衬底和在衬底上方延伸的半导体鳍片结构的半导体形貌; 在半导体拓扑的暴露表面上形成栅极电介质; 在半导体形貌上图案化掩模，使得仅限定限定要形成栅电极的位置的栅极电介质的选择部分; 以及在所述栅极电介质的所述选择部分上镀覆金属材料以在所述鳍结构的一部分上形成栅电极。
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公开(公告)号：US20090130845A1
公开(公告)日：2009-05-21
申请号：US11942393
申请日：2007-11-19
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , C25D3/38 , C25D5/34 , H01L21/2885 , H01L21/76846 , H01L21/76873 , H01L21/76877
摘要： A method of depositing copper directly onto a tantalum alloy layer of an on-chip copper interconnect structure, which includes electrodepositing copper from a neutral or basic electrolyte onto a surface of a tantalum alloy layer, in which the tantalum alloy layer is deposited on a substrate of the on-chip copper interconnect structure, and in which the copper nucleates onto the surface of the tantalum alloy layer without use of a seed layer to form a copper conductor.
摘要翻译： 一种将铜直接沉积在片上铜互连结构的钽合金层上的方法，该方法包括将铜从中性或碱性电解质电沉积到钽合金层的表面上，其中钽合金层沉积在基底上 的芯片铜互连结构，并且其中铜不会使用种子层成核形成铜导体的钽合金层的表面。
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公开(公告)号：US09347147B2
公开(公告)日：2016-05-24
申请号：US13608386
申请日：2012-09-10
IPC分类号： C03C15/00 , C25D17/00 , G01N27/403 , G01N27/404 , C25D17/12 , C25D21/12
CPC分类号： C25D17/007 , C25D17/12 , C25D21/12 , G01N27/403 , G01N27/404
摘要： An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.
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公开(公告)号：US08940149B2
公开(公告)日：2015-01-27
申请号：US13604060
申请日：2012-09-05
申请人： Shafaat Ahmed , Hariklia Deligianni
发明人： Shafaat Ahmed , Hariklia Deligianni
摘要： Solutions and processes for electrodepositing gallium or gallium alloys includes a plating bath free of complexing agents including a gallium salt, an indium salt, a combination thereof, and a combination of any of the preceding salts with copper, an acid, and a solvent, wherein the pH of the solution is in a range selected from the group consisting of from about zero to about 2.6 and greater than about 12.6 to about 14. An optional metalloid may be included in the solution.
摘要翻译： 用于电镀镓或镓合金的溶液和方法包括不含络合剂的镀浴，所述配合剂包括镓盐，铟盐，其组合以及任何前述盐与铜，酸和溶剂的组合，其中 溶液的pH在选自约0至约2.6且大于约12.6至约14的范围内。溶液中可包含任选的准金属。
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公开(公告)号：US20130183553A1
公开(公告)日：2013-07-18
申请号：US13349255
申请日：2012-01-12
申请人： Hariklia Deligianni , Harold J. Hovel , Fei Liu
发明人： Hariklia Deligianni , Harold J. Hovel , Fei Liu
CPC分类号： H01M2/204 , H01G11/16 , H01M2/348 , H01M10/0436 , H01M10/052 , H01M10/0562 , H01M10/058 , H01M2200/103 , Y10T29/49108 , Y10T29/49115
摘要： A useful lifetime of an energy storage device can be extended by providing a series connection of a battery cell and an self-programming fuse. A plurality of series connections of a battery cell and an self-programming fuse can then be connected in a parallel connection to expand the energy storage capacity of the energy storage device. Each self-programming fuse can be a strip of a metal semiconductor alloy material, which electromigrates when a battery cell is electrically shorted and causes increases in the amount of electrical current therethrough. Thus, each self-programming fuse is a self-programming circuit that opens once the battery cell within the same series connection is shorted.
摘要翻译： 可以通过提供电池单元和自编程保险丝的串联连接来扩展能量存储装置的有用寿命。 然后可以并联连接电池单元和自编程保险丝的多个串联连接以扩大能量存储装置的能量存储容量。 每个自编程保险丝可以是金属半导体合金材料的条带，当电池单元电气短路并导致电流量增加时，电极会电流化。 因此，每个自编程保险丝是一个自编程电路，一旦同一串联连接中的电池单元短路，该自编程电路就会断开。
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9.发明申请APPARATUS AND METHOD FOR ELECTROCHEMICAL PROCESSING OF THIN FILMS ON RESISTIVE SUBSTRATES 审中-公开电阻基片薄膜电化学处理装置及方法公开(公告)号：US20120318673A1
公开(公告)日：2012-12-20
申请号：US13596641
申请日：2012-08-28
CPC分类号： C25D5/54 , C25D5/006 , C25D5/02 , C25D7/123 , C25D11/005 , C25D11/024 , C25D17/001 , C25F3/14 , H01L21/28079 , H01L21/2885
摘要： An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
摘要翻译： 一种电化学方法，包括：提供与导电表面电接触的125mm或更大的半导体晶片，其中所述半导体晶片的至少一部分与电解液接触，所述半导体晶片用作第一电极; 在所述电解液中提供第二电极，所述第一和第二电极连接到电源的相对端; 并且在第一和第二电极之间施加用作为电流的光源照射半导体晶片的表面。 本发明还涉及一种包括光源和用于进行电化学过程的电化学组分的设备。
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公开(公告)号：US20120055801A1
公开(公告)日：2012-03-08
申请号：US12874504
申请日：2010-09-02
申请人： Shafaat Ahmed , Hariklia Deligianni
发明人： Shafaat Ahmed , Hariklia Deligianni
IPC分类号： C25D3/54
摘要： Solutions and processes for electrodepositing gallium or gallium alloys includes a plating bath free of complexing agents including a gallium salt, an indium salt, a combination thereof, and a combination of any of the preceding salts with copper, an acid, and a solvent, wherein the pH of the solution is in a range selected from the group consisting of from about zero to about 2.6 and greater than about 12.6 to about 14. An optional metalloid may be included in the solution.
摘要翻译： 用于电镀镓或镓合金的溶液和方法包括不含络合剂的镀浴，所述配合剂包括镓盐，铟盐，其组合以及任何前述盐与铜，酸和溶剂的组合，其中 溶液的pH在选自约0至约2.6且大于约12.6至约14的范围内。溶液中可包含任选的准金属。
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