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    Nano-enabled memory devices and anisotropic charge carrying arrays
    1.
    发明授权
    Nano-enabled memory devices and anisotropic charge carrying arrays 有权
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US07595528B2

    公开(公告)日：2009-09-29

    申请号：US11018572

    申请日：2004-12-21

    申请人： Xiangfeng Duan ,  Calvin Y. H. Chow ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    发明人： Xiangfeng Duan ,  Calvin Y. H. Chow ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    IPC分类号： H01L29/788

    CPC分类号： G11C11/56 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/936 ,  Y10S977/943

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    Nano-enabled memory devices and anisotropic charge carrying arrays
    2.
    发明授权
    Nano-enabled memory devices and anisotropic charge carrying arrays 有权
    具有纳米功能的存储器件和各向异性带电载体阵列

    公开(公告)号：US07382017B2

    公开(公告)日：2008-06-03

    申请号：US11695728

    申请日：2007-04-03

    申请人： Xiangfeng Duan ,  Calvin Y. H. Cho ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    发明人： Xiangfeng Duan ,  Calvin Y. H. Cho ,  David L. Heald ,  Chunming Niu ,  J. Wallace Parce ,  David P. Stumbo

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    摘要： Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    摘要翻译： 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米的群体包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了一种用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    MEMS DEVICES HAVING IMPROVED UNIFORMITY AND METHODS FOR MAKING THEM
    8.
    发明申请
    MEMS DEVICES HAVING IMPROVED UNIFORMITY AND METHODS FOR MAKING THEM 失效
    具有改进的均匀性的MEMS器件及其制造方法

    公开(公告)号：US20090009444A1

    公开(公告)日：2009-01-08

    申请号：US11773357

    申请日：2007-07-03

    申请人： David L. Heald ,  Fan Zhong ,  Philip Don Floyd

    发明人： David L. Heald ,  Fan Zhong ,  Philip Don Floyd

    IPC分类号： G09G3/34 ,  B05D5/12 ,  G02F1/21

    CPC分类号： G02B26/001 ,  B81B3/0072 ,  B81B2201/047

    摘要： Disclosed is a microelectromechanical system (MEMS) device and method of manufacturing the same. In one aspect, MEMS such as an interferometric modulator include one or more elongated interior posts and support rails supporting a deformable reflective layer, where the elongated interior posts are entirely within an interferometric cavity and aligned parallel with the support rails. In another aspect, the interferometric modulator includes one or more elongated etch release holes formed in the deformable reflective layer and aligned parallel with channels formed in the deformable reflective layer defining parallel strips of the deformable reflective layer.

    摘要翻译： 公开了一种微机电系统（MEMS）装置及其制造方法。 在一个方面，诸如干涉式调制器的MEMS包括一个或多个细长的内部柱和支撑可变形的反射层的支撑轨道，其中细长的内部柱完全在干涉式空腔内并与支撑轨平行排列。 在另一方面，干涉式调制器包括形成在可变形反射层中的一个或多个细长蚀刻释放孔，并且与形成在可变形反射层中形成的沟道平行排列，所述可变形反射层限定可变形反射层的平行条带。

    V-MOS imaging array
    9.
    发明授权
    V-MOS imaging array 失效
    V-MOS成像阵列

    公开(公告)号：US4173765A

    公开(公告)日：1979-11-06

    申请号：US909907

    申请日：1978-05-26

    申请人： David L. Heald ,  Teh-Hsuang Lee ,  Rajinder P. Khosla

    发明人： David L. Heald ,  Teh-Hsuang Lee ,  Rajinder P. Khosla

    IPC分类号： H01L27/144 ,  H01L27/146 ,  H01L29/78 ,  H01L27/14

    CPC分类号： H01L27/14603 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/7827 ,  H01L27/14609

    摘要： A solid state image sensing device comprises an array of picture sensing elements which are MOS transistors formed on a bulk of semiconductor material. The transistors are of a V-MOS configuration and have respective sources, V-shaped gates, and drains. The source-to-bulk diode of a V-MOS picture sensing element functions as a photodiode and is disposed near the surface of the array to receive a respective portion of imagewise illumination. In a preferred embodiment, the drain of the V-MOS picture sensing element is buried in the bulk directly beneath its respective source. The source, in conjunction with its gate, acts as a multiplex switch for the photodiode.

    摘要翻译： 固态图像感测装置包括形成在大量半导体材料上的MOS晶体管阵列的图像感测元件。 晶体管具有V-MOS结构，并具有各自的源极，V形栅极和漏极。 V-MOS图像感测元件的源到体二极管用作光电二极管并且被布置在阵列的表面附近以接收成像照明的相应部分。 在优选实施例中，V-MOS图像感测元件的漏极直接埋在其各自的源的正下方。 源极与其栅极一起用作光电二极管的多路开关。

    Signal equalization in quadrilinear imaging CCD arrays
    10.
    发明授权
    Signal equalization in quadrilinear imaging CCD arrays 失效
    四线成像CCD阵列中的信号均衡

    公开(公告)号：US4482909A

    公开(公告)日：1984-11-13

    申请号：US404179

    申请日：1982-08-02

    申请人： David L. Heald

    发明人： David L. Heald

    IPC分类号： H01L27/148 ,  H01L29/78 ,  G11C19/28 ,  H01L27/14 ,  H01L31/00

    CPC分类号： H01L27/14825

    摘要： In the operation of a high density quadrilinear CCD imaging array, photogenerate charge is transferred from the photosites, transversely through one inner CCD register to a second outer CCD register, before clocking the CCD registers. During the transfer from the inner to the outer registers, the signal charge passes through a region defined by boundaries spaced relatively widely to a region in which the boundaries are required to be spaced closely. In the latter region, two dimensional fringing fields from the boundaries elevate the minimum potential which defines the signal charge path and creates a potential step which traps a significant percentage of the signal charge. This trapping creates a large offset between the output signals from the inner and outer register. The concept proposed is to use a fat zero, i.e., an intentionally introduced small packet of charge, injected into the input of both the inner and outer CCD registers in order to totally eliminate the offset. The input structure for fat zero injection would be designed so that the size of the fat zero would be determined by the same factors creating the potential step, thereby totally eliminating any charge loss from the signal packet during the initial transfer from the photosites, and eliminating any dependance on processing variations.

    摘要翻译： 在高密度四线CCD成像阵列的操作中，在对CCD寄存器进行计时之前，将光生电荷从光电子元件横向通过一个内部CCD寄存器传输到第二个外部CCD寄存器。 在从内部寄存器到外部寄存器的传输期间，信号电荷通过由相对广泛地间隔的边界限定的区域到需要间隔的区域。 在后一个区域中，来自边界的二维边缘场提高了定义信号电荷路径的最小电位，并产生了陷阱相当大百分比的信号电荷的电位。 这种捕获在内部寄存器和外部寄存器的输出信号之间产生较大的偏移量。 所提出的概念是将脂肪零，即有意引入的小包电荷注入到内部和外部CCD寄存器的输入中，以便完全消除偏移。 脂肪零注入的输入结构将被设计成使脂肪零点的大小由相同的因素确定，从而产生潜在的步骤，从而完全消除了在从白光初始转移过程中信号包的任何电荷损失，并消除 任何依赖于处理变化。