公开(公告)号：US20110073904A1

公开(公告)日：2011-03-31

申请号：US12923469

申请日：2010-09-23

申请人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

发明人： Youichi Ashida ,  Norihito Tokura ,  Shigeki Takahashi ,  Yoshiaki Nakayama ,  Satoshi Shiraki ,  Kouji Senda

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66128 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

摘要： A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.

摘要翻译： 半导体器件包括：SOI衬底; 半导体元件，其具有设置在所述SOI衬底的有源层中的第一和第二杂质层，所述第二杂质层围绕所述第一杂质层; 以及设置在与SOI衬底的嵌入式绝缘膜相邻的有源层的一部分中的多个第一和第二导电类型区域。 交替地布置第一和第二导电类型区域。 第一和第二导电类型区域具有对应于半导体元件的布局。

公开(公告)号：US07799667B2

公开(公告)日：2010-09-21

申请号：US12219008

申请日：2008-07-15

申请人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

发明人： Satoshi Shiraki ,  Yoshiaki Nakayama ,  Shoji Mizuno ,  Takashi Nakano ,  Akira Yamada

IPC分类号： H01L21/336

CPC分类号： H01L29/7824 ,  H01L21/26586 ,  H01L21/76286 ,  H01L21/763 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/0696 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7831 ,  H01L29/7835

摘要： A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.

摘要翻译： 半导体器件包括：具有主平面的半导体衬底; 设置在主平面上的基部区域; 源区域，其设置在所述基底区域中的所述主平面上，以比所述基底区域浅; 漏极区域，设置在所述主平面上，并且与所述基极区域间隔开; 设在主平面上的沟槽; 通过沟槽栅极绝缘膜设置在沟槽中的沟槽栅电极; 通过平面栅极绝缘膜设置在半导体衬底的主平面上的平面栅电极; 以及杂质扩散区域，其具有高浓度的杂质，并且设置在基极区域的一部分中，作为面向平面栅电极的沟道区域。

公开(公告)号：US07298020B2

公开(公告)日：2007-11-20

申请号：US10797081

申请日：2004-03-11

申请人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

发明人： Syuji Asano ,  Yoshiaki Nakayama ,  Koji Eguchi

IPC分类号： H01L29/00

CPC分类号： H01L28/24 ,  H01L21/8221 ,  H01L27/0688

摘要： A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.

摘要翻译： 在半导体衬底（1）上的绝缘膜（10）上形成导线（12）。 线（12）由氮化硅膜（14），无机SOG膜（20）和TEOS膜（21）覆盖。 在TEOS膜（21）的上表面上形成有铬硅（CrSi）的薄膜电阻元件（30）。 连接薄膜电阻元件（30）形成区域下方的TEOS薄膜（21）的上表面上的台阶的局部最大值和最小点的线的锐角（锥角）与表面 的基板（1）设定为10°以下。

公开(公告)号：US6104076A

公开(公告)日：2000-08-15

申请号：US748896

申请日：1996-11-15

申请人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L21/336 ,  H01L21/8249 ,  H01L27/02 ,  H01L27/06 ,  H01L27/085 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

公开(公告)号：US5512357A

公开(公告)日：1996-04-30

申请号：US43973

申请日：1993-04-07

申请人： Kazuhiko Shimura ,  Yoshiaki Nakayama

发明人： Kazuhiko Shimura ,  Yoshiaki Nakayama

IPC分类号： D01D5/11 ,  D01F6/06 ,  D04H1/42 ,  D04H3/16 ,  B32B5/16 ,  D02G3/00 ,  D04H1/58

CPC分类号： D01F6/06 ,  D01D5/11 ,  D04H1/4291 ,  D04H1/4382 ,  D04H1/4391 ,  D04H3/16 ,  Y10T428/2924 ,  Y10T428/2927 ,  Y10T442/608

摘要： The present invention relates to a polypropylene three-dimensional plexifilamentary fiber, a method of manufacturing same, and a nonwoven fabric composed of the above fiber.The plexifilamentary fiber in accordance with the present invention has a three-dimensional plexifilamentary structure, and is characterized in that the fiber has a microwave birefringence of 0.07 or more. As a result, a dimensional stability under heating of the plexifilamentary fiber in accordance with the present invention is extremely high. Moreover, it is possible to obtain a plexifilamentary fiber having a high spreadability by adding a spreading agent to the plexifilamentary fiber. A nonwoven fabric made of such plexifilamentary fiber has a high thermal dimensional stability, and as a result, the nonwoven fabric in accordance with the present can be usefully used in a wrapping material having a heat resistance and air permeability, apparel having heat resistance and moisture permeability, a heat resistance paper, and engineering and building materials or the like.

摘要翻译： 聚丙烯三维丛状纤维及其制造方法技术领域本发明涉及聚丙烯三维丛状纤维，及其制造方法。 根据本发明的丛状纤维具有三维丛状结构，其特征在于，所述纤维的微波双折射为0.07以上。 结果，根据本发明的丛状纤维的加热下的尺寸稳定性非常高。 此外，通过向丛状纤维增加铺展剂，可以获得具有高铺展性的丛状纤维。 由这种丛状纤维制成的无纺布具有高的热尺寸稳定性，结果，根据本发明的无纺布可以有效地用于具有耐热性和透气性的包装材料，具有耐热性和水分的衣服 透气性，耐热性纸，以及工程和建筑材料等。

公开(公告)号：US5436074A

公开(公告)日：1995-07-25

申请号：US982055

申请日：1992-11-25

申请人： Kazuhiko Shimura ,  Yoshiaki Nakayama

发明人： Kazuhiko Shimura ,  Yoshiaki Nakayama

IPC分类号： D01D5/11 ,  D01F6/06 ,  D01F6/00

CPC分类号： D01D5/11 ,  D01F6/06 ,  Y10T428/29 ,  Y10T428/2913 ,  Y10T428/2922 ,  Y10T428/2973 ,  Y10T428/2978

摘要： A polypropylene three-dimensional plexifilamentary fiber having a microwave birefringence of 0.07 or more and an Mw/Mn of 4.3 or less. Although a spreading agent is not included in this fiber, the fiber has a superior fiber spreadability and dimensional stability. The fiber in accordance with the present invention can be spun from a dope composed of an isotactic polypropylene having an Mw/Mn of 4.3 or less and an MFR of 20 or less, and a halogenated hydrocarbon, by a flash spinning technique. Further, the present invention provides a spinning dope and a method of manufacturing the fiber which effectively prevent ozone layer destruction by using a 2,2-dichloro-1,1,1-trifluoroethane, a 1,2-dichlorotrifluoroethane or a solvent blended a dichloromethane with either of the above two solvents as the halogenated hydrocarbon.

摘要翻译： 聚丙烯三维丛状纤维，其微波双折射为0.07以上，＆amp;上，＆lt; Mw /＆upbar＆Mn为4.3以下。 虽然该纤维中不包含铺展剂，但纤维具有优异的纤维铺展性和尺寸稳定性。 根据本发明的纤维可以通过闪纺技术从由具有4.3以下的＆amp;上式＆gt; Mw /＆Upbar＆Mn和MFR 20以下的全同立构聚丙烯和卤代烃组成的涂料纺丝。 此外，本发明提供纺丝原液和制造纤维的方法，其通过使用2,2-二氯-1,1,1-三氟乙烷，1,2-二氯三氟乙烷或溶剂混合来有效地防止臭氧层破坏 二氯甲烷与上述两种溶剂中的任一种作为卤代烃。

公开(公告)号：US5434749A

公开(公告)日：1995-07-18

申请号：US208113

申请日：1994-03-09

申请人： Yoshiaki Nakayama

发明人： Yoshiaki Nakayama

IPC分类号： H05K1/11 ,  H01R43/02 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00 ,  H05K3/20 ,  H05K3/32 ,  H05K3/40 ,  H05K7/02 ,  H05K7/06 ,  H01R9/00

CPC分类号： H01R12/62 ,  H01R12/523 ,  H05K1/0263 ,  H05K3/202 ,  H05K1/0393 ,  H05K1/144 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10272 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2201/2072 ,  H05K2203/167 ,  H05K3/0064 ,  H05K3/326 ,  H05K3/4084 ,  H05K3/4092 ,  Y10S439/949

摘要： This invention concerns a hybrid printed circuit board which permits easy and reliable connection between small-current circuit conductors and large-current circuit conductors. The hybrid printed circuit board of this invention comprises: an insulating substrate of synthetic resin having fixing bosses erected thereon; a flexible printed circuit sheet having small-current circuit conductors; and busbars as large-current circuit conductors; wherein the flexible printed circuit sheet is stacked and arranged on the insulating substrate so that the fixing bosses erected on the insulating substrate pass through and above the flexible printed circuit sheet, the busbars as large-current circuit conductors are put in contact with the small-current circuit conductors, and the fixing bosses are heated and deformed to fix the busbars in place.

摘要翻译： 本发明涉及一种混合印刷电路板，其允许小电流电路导体和大电流电路导体之间的容易且可靠的连接。 本发明的混合印刷电路板包括：合成树脂的绝缘基板，其上竖立有固定凸台; 具有小电流电路导体的柔性印刷电路板; 和母线作为大电流电路导体; 其中柔性印刷电路板堆叠并布置在绝缘基板上，使得竖立在绝缘基板上的固定凸台通过柔性印刷电路板上方并且在柔性印刷电路板上方，作为大电流电路导体的汇流条与小电流导体接触， 电流电路导体和固定凸台被加热和变形以将母线固定到位。

公开(公告)号：USD333153S

公开(公告)日：1993-02-09

申请号：US608958

申请日：1990-11-05

申请人： Noritaka Uchibori ,  Yoshiaki Nakayama

设计人： Noritaka Uchibori ,  Yoshiaki Nakayama

公开(公告)号：US4750032A

公开(公告)日：1988-06-07

申请号：US866332

申请日：1986-05-22

申请人： Yoshiaki Nakayama

发明人： Yoshiaki Nakayama

IPC分类号： H04N9/04 ,  H04N9/73

CPC分类号： H04N9/735

摘要： An automatic white balance adjusting system for a color video camera employs a high luminance part of the luminance signal to control automatic gain controllers for the red and blue components of the signals.

摘要翻译： 用于彩色摄像机的自动白平衡调节系统使用亮度信号的高亮度部分来控制信号的红色和蓝色分量的自动增益控制器。

公开(公告)号：US20060086449A1

公开(公告)日：2006-04-27

申请号：US11251776

申请日：2005-10-18

申请人： Yoshiaki Nakayama

发明人： Yoshiaki Nakayama

IPC分类号： B32B37/00

CPC分类号： H01L23/367 ,  H01L23/34 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor device comprising: an element portion having a heat generation portion; a control circuit portion having a control circuit for controlling the element portion; and a metal member. The element portion and the control circuit portion are adjacently disposed oh a surface portion of a semiconductor substrate. The metal member as an external electrode for the element portion is disposed directly on the element portion through an interlayer insulation film. The metal member is also disposed directly on the control circuit portion through the interlayer insulation film.

摘要翻译： 一种半导体器件，包括：具有发热部分的元件部分; 控制电路部分，具有用于控制元件部分的控制电路; 和金属构件。 元件部分和控制电路部分相邻地设置在半导体衬底的表面部分上。 作为元件部分的外部电极的金属构件通过层间绝缘膜直接设置在元件部分上。 金属构件也通过层间绝缘膜直接设置在控制电路部分上。