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    Semiconductor device and manufacturing process thereof
    7.
    发明授权
    Semiconductor device and manufacturing process thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06246105B1

    公开(公告)日：2001-06-12

    申请号：US09183594

    申请日：1998-10-30

    申请人： Yukio Morozumi ,  Takenori Asahi

    发明人： Yukio Morozumi ,  Takenori Asahi

    IPC分类号： H01L2358

    CPC分类号： H01L21/76864 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and reduces the interlayer capacitance of the device. The semiconductor device has a semiconductor substrate including a MOS device, a plurality of wiring regions formed on the semiconductor substrate, and a protective insulation film formed on the top layer of the wiring regions. The protective insulation film includes a first silicon oxide film, a second silicon oxide film formed on the first silicon oxide film, and a silicon nitride film composing the top layer. The process of forming the protective insulation film includes the following steps: forming the first silicon oxide film through a reaction between a silicon compound and at least one of oxygen and a compound containing oxygen by chemical vapor deposition method, forming the second silicon oxide film on the first silicon oxide film by a condensation polymerization reaction between a silicon compound and hydrogen peroxide by chemical vapor deposition, conducting an annealing treatment at a temperature of 350-500° C., and forming the silicon nitride film.

    摘要翻译： 一种具有提高可靠性和改进的器件特性的绝缘保护膜的半导体器件及其制造方法，其改善了平面化并降低了器件的层间电容。 半导体器件具有包括MOS器件，形成在半导体衬底上的多个布线区域和形成在布线区域的顶层上的保护绝缘膜的半导体衬底。 保护绝缘膜包括第一氧化硅膜，形成在第一氧化硅膜上的第二氧化硅膜和构成顶层的氮化硅膜。 形成保护绝缘膜的过程包括以下步骤：通过化学气相沉积法通过硅化合物与氧和含氧化合物中的至少一种之间的反应形成第一氧化硅膜，形成第二氧化硅膜 通过化学气相沉积在硅化合物和过氧化氢之间进行缩聚反应的第一氧化硅膜，在350-500℃的温度下进行退火处理，并形成氮化硅膜。

    Semiconductor integrated circuit device having internal tensile and internal compression stress
    10.
    发明授权
    Semiconductor integrated circuit device having internal tensile and internal compression stress 失效
    具有内部拉伸和内部压缩应力的半导体集成电路器件

    公开(公告)号：US06569785B2

    公开(公告)日：2003-05-27

    申请号：US10177960

    申请日：2002-06-21

    申请人： Yukio Morozumi

    发明人： Yukio Morozumi

    IPC分类号： H01L2144

    CPC分类号： H01L21/76864 ,  H01L21/2855 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76882

    摘要： A semiconductor device has a structure that is capable of reducing warping of a semiconductor wafer when the semiconductor device is manufactured. The semiconductor device is manufactured by a method including the steps for forming an interlayer dielectric film having an internal compression stress and an interlayer dielectric film having an internal tensile stress. As a result, when semiconductor devices are manufactured, the tensile stress and the compression stress act on the semiconductor wafer. As a consequence, the overall stress that acts on the semiconductor wafer are reduced to a small level or to zero, and thus warping of the semiconductor wafer is reduced or eliminated when semiconductor devices are manufactured.

    摘要翻译： 半导体器件具有能够在制造半导体器件时减少半导体晶片翘曲的结构。 半导体器件通过包括用于形成具有内部压缩应力的层间电介质膜和具有内部拉伸应力的层间电介质膜的步骤的方法制造。 结果，当制造半导体器件时，拉伸应力和压缩应力作用在半导体晶片上。 结果，作用在半导体晶片上的总体应力被降低到小的水平或零，并且因此当制造半导体器件时，半导体晶片的翘曲被减小或消除。