公开(公告)号：US20120007227A1

公开(公告)日：2012-01-12

申请号：US13162846

申请日：2011-06-17

申请人： Yun-Rae CHO ,  Kun-Dae Yeom

发明人： Yun-Rae CHO ,  Kun-Dae Yeom

IPC分类号： H01L25/11 ,  H01L25/07

CPC分类号： H01L25/03 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32151 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

摘要翻译： 一种半导体封装，包括保护层，堆叠在保护层上的多个半导体芯片，设置在保护层上以包围半导体芯片的侧表面的内部密封剂，以及被设置成埋入内部的上部的端子 密封剂。 这里，每个半导体芯片包括有源表面，与有源表面相对的无效表面和设置在有源表面的一部分上的芯片焊盘，并且端子的上表面从内表面的上表面露出 密封剂。

公开(公告)号：US08664757B2

公开(公告)日：2014-03-04

申请号：US13162846

申请日：2011-06-17

申请人： Yun-Rae Cho ,  Kun-Dae Yeom

发明人： Yun-Rae Cho ,  Kun-Dae Yeom

IPC分类号： H01L29/66

CPC分类号： H01L25/03 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/2919 ,  H01L2224/32135 ,  H01L2224/32145 ,  H01L2224/32151 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/92165 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package including a protection layer, a plurality of semiconductor chips stacked on the protection layer, an inner encapsulant disposed on the protection layer to surround side surfaces of the semiconductor chips, and a terminal disposed to be buried in an upper portion of the inner encapsulant. Herein, each of the semiconductor chips includes an active surface, an inactive surface opposite to the active surface, and a chip pad disposed on a portion of the active surface, and an upper surface of the terminal is exposed from an upper surface of the inner encapsulant.

摘要翻译： 一种半导体封装，包括保护层，堆叠在保护层上的多个半导体芯片，设置在保护层上以包围半导体芯片的侧表面的内部密封剂，以及被设置成埋入内部的上部的端子 密封剂。 这里，每个半导体芯片包括有源表面，与有源表面相对的无效表面和设置在有源表面的一部分上的芯片焊盘，并且端子的上表面从内表面的上表面露出 密封剂。

公开(公告)号：US20080122081A1

公开(公告)日：2008-05-29

申请号：US11902260

申请日：2007-09-20

申请人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Eun-Chul Ahn

发明人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Eun-Chul Ahn

IPC分类号： H01L23/488 ,  H01L21/44

CPC分类号： H05K1/02 ,  H01L23/498 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/11009 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H05K1/09 ,  H05K3/0052 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0391 ,  H05K2201/09781 ,  H05K2203/0315 ,  H05K2203/175

摘要： According to an example embodiment, a method of fabricating an electronic device may include preparing a substrate with a first area and a second area. A metal interconnection may be formed on the substrate extending from the first area to the second area. An insulating layer may be formed on the substrate. A sacrificial pattern electrically connected to the metal interconnection and serving as a sacrificial anode for cathodic protection against corrosion of the metal interconnection may be formed on the second area. An opening to expose the metal interconnection on the first area may be formed by patterning the insulating layer. An electronic device fabricated by a method according to an example embodiment may include a substrate, a metal interconnection, an insulating layer, and/or a sacrificial pattern.

摘要翻译： 根据示例性实施例，制造电子设备的方法可以包括制备具有第一区域和第二区域的基板。 可以在从第一区域延伸到第二区域的基板上形成金属互连。 可以在基板上形成绝缘层。 电连接到金属互连并用作用于阴极保护以防止金属互连的腐蚀的牺牲阳极的牺牲图案可以形成在第二区域上。 可以通过图案化绝缘层来形成用于暴露第一区域上的金属互连的开口。 通过根据示例实施例的方法制造的电子器件可以包括衬底，金属互连，绝缘层和/或牺牲图案。

公开(公告)号：US07759795B2

公开(公告)日：2010-07-20

申请号：US11850576

申请日：2007-09-05

申请人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Chul-Yong Jang ,  Hyun-Jong Woo

发明人： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Chul-Yong Jang ,  Hyun-Jong Woo

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H05K3/4084 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/38 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/09481 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/0195 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2224/0401

摘要： Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

摘要翻译： 提供了具有提高互连层之间的可靠性的凸块互连结构的印刷电路板。 还提供了使用印刷电路板制造印刷电路板和半导体封装的方法。 根据一个实施例，印刷电路板包括形成在第一互连层和第二互连层之间的树脂层上的多个凸点。 第二互连层包括对应于凸起的上部的插入孔，使得凸起的上部从第二互连层突出。 至少一个凸块的上部包括具有大于相应插入孔的直径的直径的铆钉部分，以可靠地互连第一和第二互连层。

公开(公告)号：US07391105B2

公开(公告)日：2008-06-24

申请号：US10834083

申请日：2004-04-29

申请人： Kun-Dae Yeom

发明人： Kun-Dae Yeom

IPC分类号： H01L21/48

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plurality of center bonding pads of a semiconductor chip, at least one circuit layer connected to the first series of bonding wires and including a series of circuit layer wiring patterns, and a second series of bonding wires connecting the series of circuit layer wiring patterns and a series of wiring patterns. The stacked semiconductor package further includes a second series of wiring patterns, connected to the first series of wiring patterns, the a second series of wiring patterns and the series of circuit layer wiring patterns providing connections to adjacent lower and upper unit semiconductor packages, respectively.

摘要翻译： 单元半导体芯片和层叠半导体封装以及具有中心焊盘和至少一个电路层的制造方法，以减少接合长度。 单元半导体芯片包括连接到半导体芯片的多个中心接合焊盘的第一系列接合线，连接到第一系列接合线并包括一系列电路层布线图案的至少一个电路层，以及第二组 连接一系列电路层布线图案的一系列接合线和一系列布线图案。 叠层半导体封装还包括连接到第一系列布线图案的第二系列布线图案，第二系列布线图案和一系列电路层布线图案分别提供到相邻的下单元和上单元半导体封装的连接。

公开(公告)号：US20050046006A1

公开(公告)日：2005-03-03

申请号：US10834083

申请日：2004-04-29

申请人： Kun-Dae Yeom

发明人： Kun-Dae Yeom

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L23/52

CPC分类号： H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A unit semiconductor chip and stacked semiconductor package and method of manufacturing with center bonding pads and at least one circuit layer to reduce the length of bonding. The unit semiconductor chip includes a first series of bonding wires connected to a plurality of center bonding pads of a semiconductor chip, at least one circuit layer connected to the first series of bonding wires and including a series of circuit layer wiring patterns, and a second series of bonding wires connecting the series of circuit layer wiring patterns and a series of wiring patterns. The stacked semiconductor package further includes a second series of wiring patterns, connected to the first series of wiring patterns, the a second series of wiring patterns and the series of circuit layer wiring patterns providing connections to adjacent lower and upper unit semiconductor packages, respectively.

摘要翻译： 单元半导体芯片和层叠半导体封装以及具有中心焊盘和至少一个电路层的制造方法，以减少接合长度。 单元半导体芯片包括连接到半导体芯片的多个中心接合焊盘的第一系列接合线，连接到第一系列接合线并包括一系列电路层布线图案的至少一个电路层，以及第二组 连接一系列电路层布线图案的一系列接合线和一系列布线图案。 叠层半导体封装还包括连接到第一系列布线图案的第二系列布线图案，第二系列布线图案和一系列电路层布线图案分别提供到相邻的下单元和上单元半导体封装的连接。