公开(公告)号：US20080098973A1

公开(公告)日：2008-05-01

申请号：US11815201

申请日：2006-03-17

申请人： Yusuke Niwa ,  Kenjiro Matsushita ,  Teruyoshi Mihara ,  Kohji Masuda ,  Hiroyuki Kaneko ,  Norihiko Kiritani

发明人： Yusuke Niwa ,  Kenjiro Matsushita ,  Teruyoshi Mihara ,  Kohji Masuda ,  Hiroyuki Kaneko ,  Norihiko Kiritani

IPC分类号： F02P23/04

CPC分类号： F02P23/02 ,  F02P23/04

摘要： The disclosure relates to a photoconductive ignition system including a photoconductor configured to contact an oxidant-fuel gas mixture, and a light source providing irradiating light to a surface of the photoconductor. The photoconductor absorbs at least some of the light from the light source, which causes a variation in electrical potential at the surface of the photoconductor, thereby igniting the oxidant-fuel gas mixture. The disclosure further relates to a method of activating an oxidant-fuel gas mixture by exposing a photoconductor surface to the gas mixture and irradiating the surface with a light source emitting light at a wavelength corresponding to an energy level greater than a band gap energy level of the photoconductor, thereby activating the gas mixture in a combustion reaction.

摘要翻译： 本发明涉及一种光导点火系统，其包括配置成接触氧化剂 - 燃料气体混合物的光电导体和向感光体表面提供照射光的光源。 光电导体吸收来自光源的至少一些光，这导致光电导体表面的电位变化，从而点燃氧化剂 - 燃料气体混合物。 本公开还涉及一种通过将光电导体表面暴露于气体混合物并用发射光的光源照射氧化剂 - 燃料气体混合物的方法，所述光源以对应于大于等于 光电导体，从而在燃烧反应中激活气体混合物。

公开(公告)号：US5040034A

公开(公告)日：1991-08-13

申请号：US465748

申请日：1990-01-18

申请人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

发明人： Yoshinori Murakami ,  Teruyoshi Mihara ,  Tsutomu Matsushita ,  Kenji Yao ,  Norihiko Kiritani

IPC分类号： H01L29/78

CPC分类号： H01L29/7827 ,  H01L29/7839 ,  Y10S257/902

摘要： A semiconductor device includes a semiconductor substrate as a drain region. A metal source region is located on a first surface of the substrate. The metal and the substrate constitute a Schottky junction. An insulated gate, including a gate electrode and an insulating film surrounding the gate electrode, is adjacent to the Schottky junction, such that angle formed by the Schottky junction and the insulated gate in the substrate is an acute angle. A part of the Schottky metal can be buried in the form of a pillar in the substrate, and a channel region of the Schottky junction can be formed on the pillar near the insulated gate.

摘要翻译： 半导体器件包括作为漏极区域的半导体衬底。 金属源区位于基板的第一表面上。 金属和衬底构成肖特基结。 包括栅电极和围绕栅电极的绝缘膜的绝缘栅极与肖特基结相邻，使得由肖特基结和衬底中的绝缘栅极形成的角度是锐角。 肖特基金属的一部分可以以衬底的形式被埋入，并且可以在绝缘栅极附近的柱上形成肖特基结的沟道区。

公开(公告)号：US5635742A

公开(公告)日：1997-06-03

申请号：US660211

申请日：1996-06-03

申请人： Masakatsu Hoshi ,  Teruyoshi Mihara

发明人： Masakatsu Hoshi ,  Teruyoshi Mihara

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L27/10

CPC分类号： H01L29/0696 ,  H01L29/41741 ,  H01L29/7809 ,  H01L29/41766 ,  H01L29/456

摘要： A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

摘要翻译： 横向双扩散MOSFET具有半导体基板，形成在基板上的漏极区域，形成在漏极区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，通过栅电极形成的源极和漏极开口， 形成在漏极区域下方的第一导电区域，形成在源极开口上的源极电极，形成在漏极开口上的漏电极，以及用于将漏电极连接到第一导电区域的第二导电区域。 源极和漏极开口循环布置，使得至少两排源极开口布置在相邻的漏极开口之间，以降低MOSFET的导通电阻。

公开(公告)号：USRE35405E

公开(公告)日：1996-12-17

申请号：US288731

申请日：1994-08-12

申请人： Yoshinori Murakami ,  Teruyoshi Mihara

发明人： Yoshinori Murakami ,  Teruyoshi Mihara

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/66416 ,  H01L29/66666 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/05

摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

摘要翻译： 一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁 邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

公开(公告)号：US4931846A

公开(公告)日：1990-06-05

申请号：US185387

申请日：1988-04-25

申请人： Teruyoshi Mihara

发明人： Teruyoshi Mihara

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/1095 ,  H01L29/0626 ,  H01L29/0878

摘要： A vertical MOSFET device has a first conductivity type substrate layer serving as a drain, a second conductivity type channel region extending into said substrate layer from a top surface, and a first conductivity type source region extending into the channel region from the top surface. The channel region has a peripheral subregion extending deeply into the substrate layer from the top surface under an insulated gate electrode, and a shallow central subregion shallower than the peripheral subregion. There is further provided a second conductivity type underlying layer formed under the shallow central subregion so as to form a voltage regulating diode with the channel region at a position shallower than the bottom of the peripheral subregion.

公开(公告)号：US4893158A

公开(公告)日：1990-01-09

申请号：US209237

申请日：1988-06-20

申请人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

发明人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03K17/082

CPC分类号： H01L29/7815 ,  H01L27/0251 ,  H01L27/0623 ,  H03K17/0822 ,  H01L2924/0002

摘要： A power MOSFET is provided with a protective circuit including a monitor MOSFET whose drain is connected with the drain of the power MOSFET, a monitor resistor connected betwen the sources of the power and monitor MOSFETs, and a monitor transistor for decreasing a gate voltage of the power MOSFET when a voltage across the monitor resistor exceeds a predetermined level representing a dangerous condition of the device.

摘要翻译： 功率MOSFET具有保护电路，该保护电路包括监控MOSFET，漏极与功率MOSFET的漏极连接，监控电阻连接在电源和监视器MOSFET的源极之间，监视晶体管用于降低栅极电压 当监视器电阻两端的电压超过表示设备的危险状况的预定电平时，功率MOSFET。

公开(公告)号：US4862233A

公开(公告)日：1989-08-29

申请号：US63116

申请日：1987-06-17

申请人： Tsutomu Matsushita ,  Teruyoshi Mihara

发明人： Tsutomu Matsushita ,  Teruyoshi Mihara

IPC分类号： H01L27/08 ,  H01L21/76 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/7802

摘要： Vertical MOS and another component such as CMOS are made in a single semiconductor substrate having a highly doped underlying layer and a lightly doped epitaxial surface layer of a first conductivity type. The vertical MOS includes a channel region of a second conductivity type, formed in the surface layer, and a source region of the first conductivity type, formed in the channel region. The channel region is made deep and joined with the highly doped underlying layer to form a first Zener diode for regulating a drain-source voltage. A drain electrode is formed on the bottom surface of the substrate and connected to a power supply, and a topside source electrode is connected to a load. The vertical MOS is surrounded, and separated from the CMOS, by a grounded guard ring region of the second conductivity type, formed in the surface layer. The guard ring region is also made deep and joined with the underlying layer.

摘要翻译： 垂直MOS和诸如CMOS的另一部件在具有高掺杂的下层和具有第一导电类型的轻掺杂外延表面层的单个半导体衬底中制成。 垂直MOS包括形成在表面层中的第二导电类型的沟道区域和形成在沟道区域中的第一导电类型的源极区域。 沟道区域被制成深并与高度掺杂的下层连接，以形成用于调节漏极 - 源极电压的第一齐纳二极管。 漏极电极形成在基板的底面上，与电源连接，顶侧的源电极与负载连接。 垂直MOS通过形成在表面层中的第二导电类型的接地保护环区域被包围并与CMOS分离。 保护环区域也是深层的，并与底层相连。

公开(公告)号：US4314226A

公开(公告)日：1982-02-02

申请号：US109489

申请日：1980-01-04

申请人： Takeshi Oguro ,  Teruyoshi Mihara ,  Tamotsu Tominaga ,  Masami Takeuchi

发明人： Takeshi Oguro ,  Teruyoshi Mihara ,  Tamotsu Tominaga ,  Masami Takeuchi

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/147 ,  H01L29/84

摘要： A pressure sensor having a silicon diaphragm whose opposite surfaces are subjected to fluid pressures for measurement. The diaphragm includes a diffused resistor as a pressure-sensitive element on a silicon base, a protective layer composed of a silicon epitaxial layer opposite in conductive type to the resistor and formed on the diffused resistor in order to prevent the resistor from being exposed to a corresponding fluid pressure, and an electrically insulating layer formed on an outer surface of the protective layer.

摘要翻译： 一种具有硅膜片的压力传感器，其相对表面经受用于测量的流体压力。 隔膜包括作为硅基底上的压敏元件的扩散电阻器，由与电阻器相反的导电类型的硅外延层构成的保护层，并形成在扩散电阻器上，以防止电阻器暴露于 相应的流体压力，以及形成在保护层的外表面上的电绝缘层。

公开(公告)号：US5682048A

公开(公告)日：1997-10-28

申请号：US648965

申请日：1996-05-17

申请人： Toshiro Shinohara ,  Masakatsu Hoshi ,  Teruyoshi Mihara

发明人： Toshiro Shinohara ,  Masakatsu Hoshi ,  Teruyoshi Mihara

IPC分类号： H01L21/768 ,  H01L21/336 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7809 ,  H01L29/0696 ,  H01L29/4238 ,  H01L2924/0002

摘要： A semiconductor structure having a plurality of drivers in and on the same semiconductor substrate is arranged to increase the density of integrated components and reduce the on resistance. The semiconductor structure employs a double layer interconnection structure having source and drain electrodes at two different levels, and an insulated gate electrode in a groove formed the semiconductor substrate. Each drain lead region having a low resistivity material extends from the upper surface of the substrate to a low resistivity buried layer. Each drain opening is surrounded by a source zone formed with a series of source holes or a long and narrow source slot, and this basic pattern is regularly repeated in a plane.

摘要翻译： 布置具有在同一半导体衬底中的多个驱动器的半导体结构以增加集成部件的密度并降低导通电阻。 半导体结构采用具有两个不同电平的源极和漏极的双层互连结构，并且在形成半导体衬底的沟槽中形成绝缘栅电极。 具有低电阻率材料的每个漏极引线区域从衬底的上表面延伸到低电阻率掩埋层。 每个排水开口由形成有一系列源孔或长而窄的源槽的源区围绕，并且该基本图案在平面中有规律地重复。

公开(公告)号：US4922317A

公开(公告)日：1990-05-01

申请号：US81391

申请日：1987-08-04

申请人： Teruyoshi Mihara

发明人： Teruyoshi Mihara

IPC分类号： H01L27/08 ,  H01L27/092

CPC分类号： H01L27/0921

摘要： A CMOS device having an nMOS formed in a p-type substrate region, and a pMOS formed in an n-type substrate region is provided with a Schottky barrier junction for collecting holes injected into the n-type substrate region, to prevent latch-up. The Schottky barrier junction is formed by a metal electrode and the n-type substrate region, and is located between the pMOS and the nMOS.

摘要翻译： 具有形成在p型衬底区域中的nMOS和形成在n型衬底区域中的pMOS的CMOS器件设置有用于收集注入到n型衬底区域中的空穴的肖特基势垒结，以防止闩锁 。 肖特基势垒结由金属电极和n型衬底区域形成，位于pMOS和nMOS之间。