公开(公告)号：WO2008101095A2

公开(公告)日：2008-08-21

申请号：PCT/US2008/053986

申请日：2008-02-14

Applicant: CUBIC WAFER, INC. ,  WYMAN, Theodore, J. ,  TREZZA, John

Inventor： WYMAN, Theodore, J. ,  TREZZA, John

IPC: H03K19/0185

CPC classification number: H03K19/018585

Abstract: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver.

Abstract translation: 驱动器电路包括一组可选择的驱动器，每个驱动器具有单独的驱动能力，所述驱动器可选择使得i）当驱动器的子集被选择时，驱动器将以第一驱动级别驱动信号，以及ii） 当驱动器的子集和至少一个额外的驱动器被选择时，由至少一个附加驱动器所提供的驱动级别的驱动器将驱动器的驱动程度大于第一级别的级别。

公开(公告)号：WO2006138490A3

公开(公告)日：2006-12-28

申请号：PCT/US2006/023362

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John ,  MISRA, Abhay

Inventor： TREZZA, John ,  MISRA, Abhay

IPC: H01L21/44

Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back- end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

公开(公告)号：WO2008129423A2

公开(公告)日：2008-10-30

申请号：PCT/IB2008/001612

申请日：2008-06-19

Applicant: CUFER ASSET LTD. L.L.C. ,  TREZZA, John

Inventor： TREZZA, John

IPC: C23C18/16 ,  C23C18/18 ,  C23C18/31 ,  C25D5/02 ,  C25D7/12

CPC classification number: C25D5/02 ,  C23C18/1603 ,  C23C18/165 ,  C23C18/1653 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76898 ,  H01L2221/1089

Abstract: A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10µm and a depth of greater than about 50µm, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal.

Abstract translation: 一种方法包括使用沉积技术将第一导电材料沉积到材料中形成的通孔中，该通孔在材料表面的直径小于约10μm，深度大于约50μm，因此 在通孔内形成种子层，然后通过用第二导电材料无电地电镀种子层而在通孔形成和产生增厚层之间的通孔内进行任何活化过程，在种子层的顶部上产生增厚层， 然后将导体金属电镀到增稠层上，直到通孔内的增稠层界定的体积被导体金属填充。

公开(公告)号：WO2006138492A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023364

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John ,  CALLAHAN, John ,  DUDOFF, Gregory

Inventor： TREZZA, John ,  CALLAHAN, John ,  DUDOFF, Gregory

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/0014 ,  H01S5/0201 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of the second chip being a material that is malleable, bringing the aligned electrically conductive contact of the first chip into contact with the corresponding electrically conductive contact on the second chip, elevating the contact of the chips to a temperature that is below a liquidus temperature for both the rigid material and the material that is malleable while applying pressure to the chips so as to cause the rigid material to penetrate the malleable material and form an electrically conductive connection, and, following the forming of the electrically conductive connection, cooling the contacts to an ambient temperature.

Abstract translation: 将两个芯片彼此物理和电连接的方法包括将第一芯片的导电触点与第二芯片上的对应导电触点对准，第一芯片的导电触点是刚性材料，并且导电触点 第二芯片是具有延展性的材料，使得第一芯片的对齐的导电触点与第二芯片上的对应的导电触点接触，将芯片的接触升高到低于液相线温度的温度 刚性材料和材料都是可塑的，同时向芯片施加压力，以使刚性材料穿透可延展材料并形成导电连接，并且在形成导电连接之后，将触点冷却 环境温度。

公开(公告)号：WO2006138491A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023363

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L23/48

CPC classification number: H01L24/94 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract translation: 在具有邻接衬底的掺杂半导体材料的半导体芯片上执行的方法包括通过从衬底的外侧向掺杂半导体材料延伸的至少部分衬底形成第一通孔，第一通孔具有壁表面和 将第一导电材料引入第一通孔中以形成导电路径，从半导体芯片的掺杂部分的外表面延伸到底部，产生与第一通孔对准的第二通孔， 并将第二导电材料引入第二通孔中，以便产生导电路径。

公开(公告)号：WO2006138457A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023297

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6616 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/75305 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24174 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract translation: 一种装置具有彼此连接的两块基板材料，两个板包括彼此连接的一对触点，该一对触点具有将第一区域与第二区域分开的形状。

公开(公告)号：WO2008101093A1

公开(公告)日：2008-08-21

申请号：PCT/US2008/053982

申请日：2008-02-14

Applicant: CUBIC WAFER, INC. ,  CALLAHAN, John ,  TREZZA, John

Inventor： CALLAHAN, John ,  TREZZA, John

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the phototresist and plated metal until all of the exposed seed layer has been removed.

Abstract translation: 一种方法涉及对位于包含沉积种子层的晶片上的光致抗蚀剂进行图案化蚀刻，以暴露种子层的部分，对晶片进行电镀，使得电镀金属仅累积在暴露的种子层上 直到电镀金属达到种子层上方的高度，该高度至少等于种子层的厚度，除去固体光刻胶，以及去除通过除去光致抗蚀剂和电镀金属而暴露的种子层，直到所有暴露的种子层 已被删除。

公开(公告)号：WO2006138489A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023361

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L21/00

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/45111 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A chip unit has a stack of at least two electronic chips stacked one on top of the other, a through-chip connection within the stack, the through chip connection including a bounding material having an inner and outer perimeter, the inner perimeter defining an interior volume longitudinally extending through at least one of the at least two chips and at least partially into another of the at least two chips so as to form a tube extending between the one and the other of the chips, and an amount of working fluid hermetically sealed within the tube, the working fluid having a volume and being at a pressure such that the working fluid and tube will operate as a heat pipe and transfer heat from the stack of chips to the working fluid.

Abstract translation: 芯片单元具有堆叠在一起的另一个的至少两个电子芯片的堆叠，堆叠内的贯穿芯片连接，所述贯穿芯片连接包括具有内部和外部周边的边界材料，所述内部周边限定内部 纵向延伸穿过所述至少两个芯片中的至少一个并且至少部分地进入所述至少两个芯片中的另一个，以形成在所述一个和另一个芯片之间延伸的管，并且一定量的工作流体密封 在管内，工作流体具有体积并且处于压力，使得工作流体和管将作为热管进行操作，并将热量从芯片堆传递到工作流体。

公开(公告)号：WO2006138426A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023250

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  CALLAHAN, Jon ,  TREZZA, John ,  DUDOFF, Gregory

Inventor： CALLAHAN, Jon ,  TREZZA, John ,  DUDOFF, Gregory

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.

Abstract translation: 芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层，以及在阻挡层上方的可延展材料。 替代的芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层以及阻挡层上的刚性材料。

公开(公告)号：WO2008116230A2

公开(公告)日：2008-09-25

申请号：PCT/US2008/064136

申请日：2008-05-19

Applicant: CUFER ASSET LTD. L.L.C. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/5387 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0652 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A module has at least two ICs connected to each other such that they lie in different planes and are arranged as a first stack of ICs, a third IC is connected to at least one of the at least two ICs, wherein the third IC is off plane from both of the at least two ICs.

Abstract translation: 模块具有彼此连接的至少两个IC，使得它们位于不同的平面中并且被布置为IC的第一堆叠，第三IC连接到至少两个IC中的至少一个，其中第三IC关闭 从两个至少两个IC的平面。