公开(公告)号：WO2021158341A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/013124

申请日：2021-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： WANG, Zhongze ,  GAO, Yandong ,  LI, Xia ,  LU, Ye ,  ZHU, Xiaochun ,  CHEN, Xiaonan

IPC: G11C7/10 ,  G11C11/412 ,  G11C11/419 ,  G11C7/12 ,  G11C5/02 ,  G11C8/16 ,  G11C27/02

Abstract: A memory circuit that includes an array of compute in memory (CIM) NAND or NOR 8T-SRAM memory bitcells comprising shared pre-load line and shared activation line. Each compute in memory (CIM) NAND or NOR 8T-SRAM memory bitcell includes a six-transistor (6T) SRAM circuit configuration, a first transistor coupled to the six-transistor (6T) SRAM circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：WO2021150397A1

公开(公告)日：2021-07-29

申请号：PCT/US2021/013084

申请日：2021-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Junjing ,  LU, Ye ,  FENG, Peijie ,  TANG, Chenjie ,  ZHU, Xiaochun

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/0922 ,  H01L27/1104 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Certain aspects of the present disclosure relate to a gate-all-around (GAA) semiconductor device. A GAA semiconductor device includes a plurality of nanosheet stack structures disposed vertically above a horizontal plane of a substrate, wherein: each nanosheet stack structure of the plurality of nanosheet stack structures comprises one or more nanosheets; the one or more nanosheets of a first nanosheet stack structure (206a) of the plurality of nanosheet stack structures comprise a first semiconductor material; and the one or more nanosheets of a second nanosheet stack structure (206b, 206c) of the plurality of nanosheet stack structures comprise a second semiconductor material different from the first semiconductor material.

公开(公告)号：WO2013166116A1

公开(公告)日：2013-11-07

申请号：PCT/US2013/039017

申请日：2013-05-01

Applicant: QUALCOMM INCORPORATED

Inventor： GU, Shiqun ,  LAISNE, Michael ,  NOWAK, Matthew M. ,  KIM, Glen T. ,  CHAN, Mark C. ,  YAO, Hongjun

IPC: H01L21/66

CPC classification number: G01R31/3177 ,  H01L22/34 ,  H01L23/3128 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A first apparatus (102), such as a die or a semiconductor package, has signal paths (106) extending through the apparatus. The signal paths can include through vias and other components. The signal paths are operable to communicate with a second apparatus when the second apparatus is stacked with the first apparatus. The first apparatus also has pass gates (108). Each pass gate is configurable in response to a signal, to short a pair of the signal paths (106) to enable substantially simultaneous testing of the signal paths. The pass gates may be configurable to isolate the signal paths during operation of the first apparatus.

Abstract translation: 诸如管芯或半导体封装的第一设备（102）具有延伸穿过设备的信号路径（106）。 信号路径可以包括通孔和其他部件。 当第二装置与第一装置堆叠时，信号路径可操作以与第二装置通信。 第一装置还具有通过门（108）。 响应于信号可以配置每个通过门，以缩短一对信号路径（106），以使基本上同时测试信号路径。 通过门可以被配置为在第一装置的操作期间隔离信号路径。

公开(公告)号：WO2021178168A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/019330

申请日：2021-02-24

Applicant: QUALCOMM INCORPORATED

Inventor： GOPALAKRISHNA, Shankar ,  FRANCIS, Saju Cheeran Verghese ,  AVVARU, Vivekananda

IPC: H05K7/14 ,  H05K7/20

Abstract: An electronics enclosure can be a line replaceable unit for installation in a chassis having actively cooled cold plates. The electronics enclosure has a housing, heat spreaders, and moveable heat spreaders. The electronics enclosure can be positioned in the chassis with the moveable heat spreaders close to the housing and thereafter the moveable heat spreaders can be moved away from the housing to press against the cold plates. Heat from electronics within the electronics enclosure can pass from the housing, through the heat spreaders, through the moveable heat spreaders, and into the cold plates.

公开(公告)号：WO2014055777A1

公开(公告)日：2014-04-10

申请号：PCT/US2013/063297

申请日：2013-10-03

Applicant: QUALCOMM INCORPORATED

Inventor： HENDERSON, Brian M. ,  TAN, Chiew-Guan ,  UVIEGHARA, Gregory A. ,  JALILIZEINALI, Reza

IPC: H01L23/60 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5256 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014

Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second dies active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.

Abstract translation: 一个特征涉及包括至少第一集成电路（IC）管芯和第二IC管芯的多芯片模块。 第二IC芯片具有通过基板通孔电耦合到第一IC裸片的输入/输出（I / O）节点。 第二裸片有源表面还包括电连接到I / O节点并且适于保护第二IC裸片免受静电放电（ESD）引起的损坏的熔丝。 特别地，保险丝保护第二IC芯片免受由于在多芯片模块的制造期间将第一裸片电耦合到第二裸片而产生的ESD。 在将第一管芯耦合到第二管芯时，熔丝可以将由ESD产生的ESD电流旁路到地。 多芯片模块封装完成后，保险丝可能会断开。

公开(公告)号：WO2014015316A2

公开(公告)日：2014-01-23

申请号：PCT/US2013/051392

申请日：2013-07-19

Applicant: QUALCOMM INCORPORATED

Inventor： CHUA-EOAN, Lew G. ,  ZHANG, Rongtian

IPC: H01L23/34

CPC classification number: H01L22/10 ,  G06F1/206 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G07F17/326 ,  H01L22/00 ,  H01L23/34 ,  H01L23/345 ,  H01L25/0657 ,  H01L25/18 ,  H01L35/00 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172

Abstract: Some implementations provide a semiconductor package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The semiconductor package also includes a leakage sensor configured to measure a leakage current of the first die. The semiconductor package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based on the leakage current of the first die.

Abstract translation: 一些实施方式提供了一种半导体封装，其包括第一裸片和与第一裸片相邻的第二裸片。 第二模具能够加热第一模具。 半导体封装还包括配置成测量第一裸片的泄漏电流的泄漏传感器。 半导体封装还包括耦合到泄漏传感器的热管理单元。 热管理单元被配置为基于第一管芯的漏电流来控制第一管芯的温度。

公开(公告)号：WO2011025894A1

公开(公告)日：2011-03-03

申请号：PCT/US2010/046855

申请日：2010-08-26

Applicant: QUALCOMM Incorporated ,  CHANDRASEKARAN, Arvind ,  HENDERSON, Brian M.

Inventor： CHANDRASEKARAN, Arvind ,  HENDERSON, Brian M.

IPC: H01L21/98 ,  H01L25/065 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L24/94 ,  H01L21/563 ,  H01L21/568 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68377 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/838 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/83

Abstract: A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes.

Abstract translation: 用于与第二晶片重构的晶片的晶片与晶片的堆叠的半导体制造工艺产生堆叠的（3D）IC。 复原晶片包括模具，模具互连和模具化合物。 堆叠时，重构晶片的管芯互连对应于第二晶片上的管芯互连。 晶圆到晶片堆叠提高了制造工艺的生产率。 重构的晶片可以包括与第二晶片中的尺寸不同的模具。 此外，重构晶片的管芯可以从具有与第二晶片不同的尺寸的晶片分离。 因此，这种晶片到晶片的制造工艺可以组合不同尺寸的模具和/或晶片。

公开(公告)号：WO2021162816A1

公开(公告)日：2021-08-19

申请号：PCT/US2021/013176

申请日：2021-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： RAE, David Fraser ,  HOLMES, John ,  HSU, Marcus ,  KANG, Kuiwon ,  SODHI, Avantika

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/42 ,  H01L23/433

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

公开(公告)号：WO2014011612A2

公开(公告)日：2014-01-16

申请号：PCT/US2013/049682

申请日：2013-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Zhongping ,  ZHAO, Lily ,  HAN, Michael

IPC: H01L23/485

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06141 ,  H01L2224/06145 ,  H01L2224/06517 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/14145 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract translation: 本公开的一些示例性实施例涉及一种半导体封装，其包括封装衬底，管芯和耦合到封装衬底和管芯的一组凸底下金属化（UBM）结构。 每个UBM结构沿其各自的横向尺寸具有非圆形横截面。 每个UBM结构包括第一较窄部分和第二较宽部分。 第一较窄部分具有第一宽度。 第二较宽部分具有大于第一宽度的第二宽度。 每个UBM结构朝向管芯的特定区域定向，使得UBM结构的第一较窄部分比UBM结构的第二较宽部分更靠近管芯的特定区域。

公开(公告)号：WO2013158721A1

公开(公告)日：2013-10-24

申请号：PCT/US2013/036907

申请日：2013-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： CHIRIAC, Victor A. ,  LISK, Durodami J. ,  RADOJCIC, Ratibor

IPC: H01L23/42 ,  H01L23/433

CPC classification number: H01L23/4275 ,  H01L23/4334 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: An apparatus has external and/or internal capacitive thermal material for enhanced thermal package management. The apparatus includes an integrated circuit (IC) package having a heat generating device. The apparatus also includes a heat spreader having a first side that is attached to the IC package. The apparatus also includes capacitive thermal material reservoirs contacting the first side of the heat spreader. The capacitive thermal material reservoirs may be disposed laterally relative to the heat generating device.

Abstract translation: 一种具有用于增强热封装管理的外部和/或内部电容热材料的装置。 该装置包括具有发热装置的集成电路（IC）封装。 该装置还包括具有附接到IC封装的第一侧的散热器。 该装置还包括接触散热器第一侧的电容式热材料储存器。 电容热材料储存器可以相对于发热装置横向设置。