公开(公告)号：WO2013172814A1

公开(公告)日：2013-11-21

申请号：PCT/US2012/037787

申请日：2012-05-14

Applicant: INTEL CORPORATION ,  GOH, Eng Huat ,  TEOH, Hoay Tien

Inventor： GOH, Eng Huat ,  TEOH, Hoay Tien

IPC: H01L23/48 ,  H01L25/065

CPC classification number: H01L24/02 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/2518 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/0105 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Abstract translation: 一种微电子封装，其具有邻近微电子器件的有源表面和侧面的第一无凸起的构建层结构和邻近微电子器件的后表面的第二无扰乱积聚层结构，其中通过第一无扰动构建形成导电路径 从微电子器件有源表面到第二无扰性积聚层结构中的导电路径的上层，并且其中邻近微电子器件背表面并延伸到微电子器件中的穿硅通孔电连接到第二无扰动积聚层 结构导电路线。

公开(公告)号：WO2013003695A2

公开(公告)日：2013-01-03

申请号：PCT/US2012/044871

申请日：2012-06-29

Applicant: INTEL CORPORATION ,  MALATKAR, Pramod ,  DELANEY, Drew W.

Inventor： MALATKAR, Pramod ,  DELANEY, Drew W.

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.

Abstract translation: 本公开涉及制造微电子封装及其制造的领域，其中微电子器件可以形成在无凸起的堆积层无芯（BBUL-C）微电子封装内，并且其中翘曲控制结构可以设置在背面 微电子器件的表面。 翘曲控制结构可以是包括至少一层高热膨胀系数材料层，包括但不限于填充的环氧树脂材料和至少一种高弹性模量材料层，例如金属层。

公开(公告)号：WO2013162519A1

公开(公告)日：2013-10-31

申请号：PCT/US2012/034798

申请日：2012-04-24

Applicant: INTEL CORPORATION ,  MANUSHAROW, Mathew, J. ,  ROY, Mihir ,  RADHAKRISHNAN, Kaladhar ,  MALLIK, Debendra ,  BURTON, Edward

Inventor： MANUSHAROW, Mathew, J. ,  ROY, Mihir ,  RADHAKRISHNAN, Kaladhar ,  MALLIK, Debendra ,  BURTON, Edward

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19106 ,  H05K1/111 ,  H05K1/141 ,  H05K2201/1003

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

Abstract translation: 本说明书涉及制造微电子结构的领域。 微电子结构可以包括具有开口的微电子衬底，其中开口可以通过微电子衬底形成，或者可以是在微电子衬底中形成的凹部。 微电子封装可以附接到微电子衬底，其中微电子封装可以包括具有第一表面和相对的第二表面的插入件。 微电子器件可以附接到插入器第一表面，并且插入器可以通过插入器第一表面附接到微电子衬底，使得微电子器件延伸到开口中。 至少一个次级微电子器件可以附接到插入件第二表面。

公开(公告)号：WO2013028194A1

公开(公告)日：2013-02-28

申请号：PCT/US2011/049087

申请日：2011-08-25

Applicant: INTEL CORPORATION ,  REFAELI, Itsik ,  SOVER, Raanan ,  ROZIC, Alberto ,  KAFRI, Ran ,  MEGAHED, Mohamed, A.

Inventor： REFAELI, Itsik ,  SOVER, Raanan ,  ROZIC, Alberto ,  KAFRI, Ran ,  MEGAHED, Mohamed, A.

IPC: H01R12/71 ,  H01R24/38 ,  H01L23/52 ,  H01L23/48

CPC classification number: B81B7/007 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01R24/50 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present disclosure relates to the field of fabricating microelectronic packages and devices, wherein a microelectronic package may be formed with an interposer with at least one microelectronic component attached to an active surface of the interposer, and at least one coaxial connector attached to an opposing attachment surface of the interposer. The microelectronic package may be attached to a substrate to form the microelectronic device, wherein the substrate includes an opening therethrough for access to the at least one coaxial connector.

Abstract translation: 本公开涉及制造微电子封装和器件的领域，其中微电子封装可以形成有插入器，其具有附接到插入器的有源表面的至少一个微电子部件，以及附接到相对附件的至少一个同轴连接器 插入器的表面。 微电子封装可以附接到衬底以形成微电子器件，其中衬底包括穿过其中的用于接近至少一个同轴连接器的开口。

公开(公告)号：WO2011090583A2

公开(公告)日：2011-07-28

申请号：PCT/US2010/059620

申请日：2010-12-09

Applicant: INTEL CORPORATION ,  PILLARISETTY, Ravi ,  JIN, Been-Yih ,  CHU-KUNG, Benjamin ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  RADOSAVLJEVIC, Marko ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  CHAU, Robert

Inventor： PILLARISETTY, Ravi ,  JIN, Been-Yih ,  CHU-KUNG, Benjamin ,  METZ, Matthew V. ,  KAVALIEROS, Jack T. ,  RADOSAVLJEVIC, Marko ,  KOTLYAR, Roza ,  RACHMADY, Willy ,  MUKHERJEE, Niloy ,  DEWEY, Gilbert ,  CHAU, Robert

IPC: H01L29/772 ,  H01L21/335

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Abstract translation: 量子阱晶体管具有锗量子阱沟道区。 含硅蚀刻停止层提供了靠近通道的栅极电介质的容易放置。 III-V族阻挡层增加了通道的应变。 沟道区上方和下方的分级硅锗层改善了性能。 多栅介质材料允许使用高k值的栅介质。

公开(公告)号：WO2011075228A3

公开(公告)日：2011-06-23

申请号：PCT/US2010/055225

申请日：2010-11-03

Applicant: INTEL CORPORATION ,  SHAH, Uday ,  CHU-KUNG, Benjamin ,  JIN, Been-Yih ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko ,  RACHMADY, Willy

Inventor： SHAH, Uday ,  CHU-KUNG, Benjamin ,  JIN, Been-Yih ,  PILLARISETTY, Ravi ,  RADOSAVLJEVIC, Marko ,  RACHMADY, Willy

IPC: H01L29/78 ,  H01L21/336

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

公开(公告)号：WO2013133827A1

公开(公告)日：2013-09-12

申请号：PCT/US2012/028126

申请日：2012-03-07

Applicant: INTEL CORPORATION ,  MA, Qing ,  SWAN, Johanna M.

Inventor： MA, Qing ,  SWAN, Johanna M.

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81192 ,  H01L2924/00013 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/10378 ,  Y10T29/49147 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present description relate to the field of fabricating microelectronic substrates. The microelectronic substrate may include a trace routing structure disposed between opposing glass layers. The trace routing structure may comprise one or more dielectric layers having conductive traces formed thereon and therethrough. Also disclosed are embodiments of a microelectronic package including a microelectronic device disposed proximate one glass layer of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects.

Abstract translation: 本说明书的实施例涉及制造微电子基板的领域。 微电子衬底可以包括布置在相对的玻璃层之间的迹线路由结构。 迹线布线结构可以包括一个或多个具有形成在其上并具有导电迹线的电介质层。 还公开了微电子封装的实施例，其包括微电子器件，微电子器件设置在微电子衬底的一个玻璃层附近，并通过多个互连与微电子衬底耦合。

公开(公告)号：WO2013095362A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066046

申请日：2011-12-20

Applicant: INTEL CORPORATION ,  LI, Zhihua ,  DHAVALESWARAPU, Hemanth K. ,  PETRINI, Joseph B. ,  DEVASENATHIPATHY, Shankar ,  ROACH, Steven B. ,  SAUCIUC, Ioan ,  DESAI, Pranav K. ,  KOSTIEW, George S. ,  SAHA, Sanjoy K.

Inventor： LI, Zhihua ,  DHAVALESWARAPU, Hemanth K. ,  PETRINI, Joseph B. ,  DEVASENATHIPATHY, Shankar ,  ROACH, Steven B. ,  SAUCIUC, Ioan ,  DESAI, Pranav K. ,  KOSTIEW, George S. ,  SAHA, Sanjoy K.

IPC: H01L21/60 ,  H01L23/48 ,  H01L23/34

CPC classification number: B23K37/003 ,  B23K3/085 ,  B23K20/023 ,  F25B21/02 ,  F25B2321/0251 ,  H01L24/13 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/291 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75502 ,  H01L2224/81203 ,  H01L2224/83203 ,  H05K3/34 ,  H01L2924/014

Abstract: Various embodiments of thermal compression bonding transient cooling solutions are described. Those embodiments include a an array of vertically separated micro channels coupled to a heater surface, wherein every outlet micro channel comprises two adjacent inlet micro channel, and wherein an inlet and outlet manifold are coupled to the array of micro channels, and wherein the heater surface and the micro channels are coupled within the same block.

Abstract translation: 描述了热压接瞬态冷却方案的各种实施例。 这些实施例包括耦合到加热器表面的垂直分离的微通道的阵列，其中每个出口微通道包括两个相邻的入口微通道，并且其中入口歧管和出口歧管联接到微通道阵列，并且其中加热器表面 并且微通道在同一块内耦合。

公开(公告)号：WO2013048455A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054329

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  JOSHI, Subhash M. ,  HATTENDORF, Michael

Inventor： JOSHI, Subhash M. ,  HATTENDORF, Michael

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

Abstract translation: 本发明涉及非平面晶体管内的形成源极/漏极结构，其中从非平面晶体管去除翅片间隔物，以便从非平面晶体管鳍片形成源/漏结构， 具有适当材料的平面晶体管鳍片以形成源极/漏极结构。

公开(公告)号：WO2012128884A2

公开(公告)日：2012-09-27

申请号：PCT/US2012/026121

申请日：2012-02-22

Applicant: INTEL CORPORATION ,  ZENG, Raymond W. ,  KAU, DerChang

Inventor： ZENG, Raymond W. ,  KAU, DerChang

IPC: G11C13/02 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/06 ,  G11C8/08 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C16/08

Abstract: The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line.

Abstract translation: 本公开涉及制造非易失性存储器件。 在至少一个实施例中，可以使用单个晶体管来驱动每个地址线，字线或位线。 可以通过这些单晶体管器件来驱动抑制电压和选择电压，这可以通过引入地址线的奇数和偶数来实现。 在一个操作实施例中，所选地址线可被驱动为选择电压，并且允许与所选地址线相同的奇数或偶数标识的地址线浮置。 奇数或偶数指定的地址线与选定的地址线不同被驱动到禁止电压，其中相邻的浮动地址线可以用作到所选地址线的屏蔽线。