公开(公告)号：EP1737282A1

公开(公告)日：2006-12-27

申请号：EP05727833.5

申请日：2005-03-29

Applicant: Mitsubishi Cable Industries, Ltd.

Inventor： AMBO, T.; Nerima Office, Mitsubishi Cable Ind. Ltd ,  FUJIWARA, S.; Nerima Office, Mitsubishi Cable Ind ,  HASEGAWA, Y.; Nerima Office, Mitsubishi Cable Ind. ,  NAKAGAWA, C.; Nerima Office, Mitsubishi Cable Ind. ,  ONO, T.; c/o Nerima Office, Mitsubishi Ind. Ltd ,  URUSHIDANI, A.; Nerima Office, MITSUBISHI Cable In ,  KASHIOKA, T.; Nerima Office, Mitsubishi Cable Ind ,  SHIMAZAWA, K.; Nerima Office, Mitsubishi Cable Ind

IPC: H05K1/02 ,  H05K3/46 ,  H02G3/16

CPC classification number: H05K3/202 ,  H01R9/2466 ,  H01R12/523 ,  H05K3/041 ,  H05K3/222 ,  H05K3/308 ,  H05K3/326 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/4611 ,  H05K13/0061 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10401 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2203/081 ,  H05K2203/082 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board with a simple structure is manufactured. A circuit board 19 has thereon a foil circuit 21 provided on a synthetic resin plate 20 formed by injection molding, made of a copper foil, and having a pattern different for circuit board 19. Anchor pins 20a projecting upward are provided on the resin plate 20 and passed through pinholes made in the foil circuit 21. The foil circuit 21 are positioned and secured to the resin plate 20. In a required portion of the resin plate 20, a terminal insertion hole 20c is provided, and receiving terminal 22 is secured to the required portion of the terminal insertion hole 20c and connected to the foil circuit 21.

Abstract translation: 制造具有简单结构的电路板。 电路板19上具有设置在由铜箔制成并具有不同于电路板19的图案的注射成型的合成树脂板20上的箔片电路21.在树脂板20上设置有向上突出的定位销20a 并通过箔片电路21中制成的针孔。箔片电路21定位并固定到树脂板20.在树脂板20的所需部分中，设置有端子插入孔20c，并且接收端子22被固定到 端子插入孔20c的所需部分并连接到箔片电路21。

公开(公告)号：EP0870325B1

公开(公告)日：2006-10-11

申请号：EP95924747.9

申请日：1995-06-29

Applicant: TESSERA, INC.

Inventor： DISTEFANO, Thomas, H. ,  SMITH, John, W.

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/48 ,  H01L23/498 ,  H01R13/24 ,  H01R12/22

CPC classification number: H01L23/4985 ,  H01L21/4839 ,  H01L23/22 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/72 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4084 ,  H05K2201/0133 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2203/063 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49158 ,  H01L2924/00 ,  H01L2224/48

Abstract: A microelectronic connection component includes a dielectric sheet (34) having an area array of elongated, strip-like leads (60). Each lead has a terminal end (66) fastened to the sheet and a tip end (68) detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer (86). The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts. A compliant dielectric material may be provided between the sheet and chip, substantially surrounding the S-shaped ribbons.

公开(公告)号：EP1628511A2

公开(公告)日：2006-02-22

申请号：EP05016596.8

申请日：2005-07-29

Applicant: Muck, Siegfried

Inventor： Muck, Siegfried

IPC: H05K3/38 ,  H05K3/24

CPC classification number: H05K3/363 ,  H01R4/024 ,  H01R12/592 ,  H01R12/721 ,  H01R12/777 ,  H05K3/3405 ,  H05K2201/062 ,  H05K2201/091 ,  H05K2201/1034 ,  H05K2201/10772 ,  H05K2201/1084 ,  H05K2201/10848

Abstract: Beschrieben ist eine Baugruppe für elektrische/elektronische Geräte, mit mindestens einem elektrisch leitenden Bauteil, insbesondere einem Kontaktstift, das in einem Kontaktbereich mittels eines dort durch ein selektives Lötverfahren aufgeschmolzenen Lotdepots mit einer Leiterbahn eines Flachbandleiters verbunden ist, wobei die Leiterbahn mit einer Ausformung versehen ist, und ein Verfahren zur Herstellung der Baugruppe.
Nachteilig bei einer bekannten Baugruppe ist, dass die gebildete Lötstelle durch eine von innen nach außen wirkende Kapillarwirkung einen ausgefransten Randbereich erhält. Es hat sich gezeigt, dass ein solch unregelmäßiger Randbereich anfällig ist für die Ausbildung von mikroskopisch feinen Rissen. Diese haben die Tendenz, sich aufgrund mechanischer oder thermischer Belastungen der Bauteile auszubreiten. Die Lebensdauer der Lötverbindung wird dadurch erheblich herabgesetzt.
Die Aufgabe der Erfindung besteht darin, eine Baugruppe der Eingangs beschriebenen Art mit Kontaktstiften von Feder- und Messerleisten bzw. Platinen- und Steckergehäusen als Bauteile zu schaffen, die so ausgestaltet sind, dass die Lötverbindungen hinsichtlich ihrer Qualität und ihres Aussehen verbessert werden. Gleichzeitig soll ein Verfahren zur Herstellung einer solchen Baugruppe mit einem geringen Energieaufwand angegeben werden.
Gelöst wird diese Aufgabe dadurch, dass das Bauteil im Kontaktbereich bei hinreichender Festigkeit eine minimierte Wärmekapazität aufweist und dass die Ausformung der Leiterbahn eine vor Beginn des Lötvorganges einen im Wesentlichen punktförmigen Kontakt zwischen der Ausformung und dem Lotdepot sicherstellende Gestalt aufweist.
Dadurch kann gezielt eine von außen nach innen wirkende Kapillarwirkung erzeugt werden. Infolge der Minimierung seiner Wärmekapazität im Kontaktbereich nimmt das Bauteil während der Erwärmung auf die vorgegebene Temperatur nur einen sehr geringen Anteil der Energie auf Insgesamt ergibt sich durch diese optimale Steuerung des Lötvorganges eine bessere Lötqualität.

Abstract translation: 模块包括通过焊料沉积物的选择性焊接而连接到柔性印刷电路的导电轨道的接触针。 接触区域中的接触销具有最小的热容量和足够的强度。 导电轨道的形状（13）使得在焊接过程之前，存在与焊料沉积物的点状接触。 焊接工艺包括独立的要求。

公开(公告)号：EP1612047A1

公开(公告)日：2006-01-04

申请号：EP05254027.5

申请日：2005-06-28

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Nakayama, Koji c/o Brother Kogyo Kabushiki Kaisha

IPC: B41J2/14 ,  H05K3/40 ,  B41J2/16

CPC classification number: H01R12/62 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1634 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  H05K1/0393 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0191 ,  H05K2201/091 ,  H05K2203/0195 ,  Y10T29/49002 ,  Y10T29/49021 ,  Y10T29/49147 ,  Y10T29/49151

Abstract: The ink jet head is provided with a piezo-electric sheet (21) having a plurality of contacts (36) distributed on a surface thereof. A flat connector is fixed so as to cover the surface of the piezo-electric sheet. A plurality of conductive spots (48a) and a plurality of conductive lines (48b) are formed on a surface of the flat connector (50). One of each of the conductive lines is connected with one of each of the conductive spots, and the plurality of conductive spots is disposed with the same distributive pattern as the plurality of contacts. The flat connector is provided with a sheet formed of an insulating material (46), and is provided with a plurality of projections (51) corresponding to the conductive spots. At least a distal end of each of the projections is covered with one of the conductive spots. The flat connector and the piezo-electric sheet are fixed such that the conductive spots make contact with the contacts of the piezo-electric sheet. Portions (53) of the flat connector having projections are thinner than the surrounding area of the flat connector.

Abstract translation: 喷墨头设置有具有分布在其表面上的多个触点（36）的压电片（21）。 扁平连接器被固定以覆盖压电片的表面。 在扁平连接器（50）的表面上形成多个导电点（48a）和多条导线（48b）。 每个导电线中的一个与每个导电点中的一个连接，并且多个导电点以与多个触点相同的分布图案设置。 扁平连接器设置有由绝缘材料（46）形成的片材，并且设置有与导电点对应的多个突起（51）。 每个突起的至少一个远端被一个导电点覆盖。 扁平连接器和压电片是固定的，使得导电点与压电片的触点接触。 具有突起的扁平连接器的部分（53）比扁平连接器的周围区域薄。

公开(公告)号：EP1421835B1

公开(公告)日：2005-10-12

申请号：EP02746740.6

申请日：2002-06-27

Applicant: 3M Innovative Properties Company

Inventor： KOSKENMAKI, David, C. ,  MILLER, Michael, N. ,  JING, Naiyong

IPC: H05K3/10 ,  H05K9/00 ,  H05B3/86

CPC classification number: H05B3/86 ,  G02F1/13439 ,  G02F1/155 ,  H05B3/286 ,  H05B2203/017 ,  H05K3/102 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/0133 ,  H05K2201/09036 ,  H05K2201/091 ,  H05K2201/09827 ,  H05K2203/0278 ,  H05K2203/1105 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method for making a fine electrically conductive grid embedded in a polymer substrate (30). The method includes the steps of providing a polymer substrate (30), forming a pattern of grooves (31) in the substrate (30), filling the grooves (31) with electrically conductive powder, and then applying heat and/or pressure to the substrate (30). The application of heat and/or pressure to the substrate (30) causes the grooves (31) to collapse inward against the conductive powder. Collapsing the grooves (31) compacts the conductive powder within the groove (31), thereby establishing a continuously conductive grid line or circuit. The narrow grid lines that result allow more light to transmit through the substrate (30). The method allows grid lines to be made with higher aspect ratios (ratio of line depth to line width) than is possible by previous methods.

公开(公告)号：EP1494277A2

公开(公告)日：2005-01-05

申请号：EP04014685.4

申请日：2004-06-23

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Kojima, Toshiyuki ,  Nakatani, Seiichi ,  Sugaya, Yasuhiro ,  Yamamoto, Yoshiyuki

IPC: H01L23/055 ,  H01L25/10

CPC classification number: H05K1/186 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/5385 ,  H01L27/14618 ,  H01L27/14643 ,  H01L27/148 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0272 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0108 ,  H05K2201/0209 ,  H05K2201/091 ,  H05K2201/10121 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: In a module with a built-in semiconductor, higher densification is achieved by disposing inner vias close to a semiconductor device. A module which has a space 107 between a first wiring layer 102a and a built-in semiconductor device 105 is obtained by: mounting the semiconductor device 105 on a first wiring layer 102a of a wiring board 103 without using a sealing resin; stacking on the circuit board an electrically insulating substrate having a through bore (inner via) 104 filled with a conductive paste and an opening for receiving the semiconductor device, and a mold release carrier having a second wiring layer 102b in the stated order; and heating and pressurizing so that the semiconductor device 105 is incorporated in a core layer 101 which is formed by curing the electrically insulating substrate.

Abstract translation: 在具有内置半导体的模块中，通过将靠近半导体器件的内部通孔布置来实现更高的致密化。 通过以下方式获得在第一布线层102a和内置半导体器件105之间具有空间107的模块：将半导体器件105安装在布线板103的第一布线层102a上，而不使用密封树脂; 在电路板上堆叠具有填充有导电浆料的通孔（内通孔）104和用于接收半导体器件的开口的电绝缘基板，以及具有按照所述顺序具有第二布线层102b的脱模载体; 加热加压，使得半导体器件105被结合在通过固化电绝缘基板而形成的芯层101中。

公开(公告)号：EP1102351A1

公开(公告)日：2001-05-23

申请号：EP00122361.9

申请日：2000-10-24

Applicant: Sumitomo Wiring Systems, Ltd.

Inventor： Nakamura, Masayoshi

IPC: H01R9/20

CPC classification number: H05K3/202 ,  H01R9/20 ,  H05K1/0298 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/091 ,  H05K2201/2072 ,  Y10S439/949

Abstract: [Object]
To provide a wire laying plate assembly which can be securely assembled by preventing a molding error of insulating plates.
[Solution]
Bosses 46 to 48 to be crimped for connection project from insulating plates 24 to 26 formed of a synthetic resin. The insulating plates 25 to 27 are formed with boss escaping portions 55 to 57 for accommodating leading ends 49 to 51 of the bosses 46 to 48 formed on different insulating plates 24 to 26 placed one over another. The boss escaping portions 55 to 57 are so formed as to gradually become deeper from their outer peripheries toward their centers. Busbars 28 to 31 are arranged between the insulating plates 24 to 27. The busbars 29 to 31 are formed with insertion holes 52 to 54. The busbars 29 to 31 are secured to the insulating plates 24 to 27 by inserting the bosses 46 to 48 through the insertion holes 52 to 54 and crimping them. In this way, a wire laying plate assembly 19 is assembled.

Abstract translation: 提供可以通过防止绝缘板的成型误差而可靠地组装的敷线板组件。 ÄSolution将Bosses 46至48压接成由合成树脂形成的绝缘板24至26的连接。 绝缘板25至27形成有用于容纳形成在彼此重叠的不同绝缘板24至26上的凸起46至48的前端部49至51的凸起部分55至57。 凸起部55-57形成为从其外周朝向其中心逐渐变深。 母线28至31布置在绝缘板24至27之间。母线29至31形成有插入孔52至54.母线29至31通过将凸起46至48插入到绝缘板24至27中而固定到绝缘板24至27 插入孔52至54并压接它们。 以这种方式，组装线缆组件19。

公开(公告)号：EP0863530A3

公开(公告)日：1999-05-06

申请号：EP98100723.0

申请日：1998-01-16

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Tonejc, Vinko

IPC: H01H50/04 ,  H05K3/20

CPC classification number: H05K3/202 ,  H01H50/021 ,  H01H50/047 ,  H01H2050/049 ,  H05K3/328 ,  H05K3/4092 ,  H05K2201/091 ,  H05K2201/10651 ,  H05K2201/2072

Abstract: Die Leiterplatte (1) besteht aus einer Kunststoff-Trägerplatte (2) und einem die Leiterbahnen der elektrischen Schaltung bildenden einstückigen Stanzgitter (3), welche über vorzugsweise heißverprägte oder ultraschallverformte Kunststoffstege (12) mechanisch fest miteinander verbunden sind. Die Leiterbahnen weisen rechtwinklig abgebogene Anschluß-(3a) und Kontaktlappen (6) zur Kontaktierung des Stecksockels (4) und der aufzunehmenden Relais (10) sowie herausgeprägte Kontaktprofile (5) für die Verbindung mit elektrischen Bauteilen (11) auf. Die aufgesteckten Relais (10) und Bauteile (11) sind ebenso wie der Stecksockel (4) vorzugsweise durch Verschweißen lötfrei mit den Leiterbahnen verbunden. Durch Aussparungen (7) in der Trägerplatte (2) entsteht für Werkzeuge ein beidseitiger Zugang zu den Trennstellen (9) im Stanzgitter (3).

公开(公告)号：EP0610360B1

公开(公告)日：1995-10-25

申请号：EP92922851.8

申请日：1992-11-01

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： BRUCKNER, Helmut ,  KÖPNICK, Siegfried ,  UGGOWITZER, Werner

IPC: H05K3/46 ,  H05K3/20

CPC classification number: H05K3/4652 ,  H05K3/3447 ,  H05K3/4038 ,  H05K3/4084 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/091 ,  H05K2203/033 ,  H05K2203/063 ,  Y10T29/49155 ,  Y10T29/49167 ,  Y10T156/1046 ,  Y10T156/1056 ,  Y10T156/109 ,  Y10T156/1093

Abstract: The description relates to a process for manufacturing an at least two-layer printed circuit with a base plate, a first conductor plane with contact areas (pads) and a second conductor plane with connecting areas (solder eyes) in which a conductive film with an adhesive layer is laminated on the base plate with the first conductor plane and the pads, whereby the adhesive layer and the conductive film has holes corresponding to the pads of the first conductor plane. The perforated conductive film with the adhesive layer is pressed on the base plate with the first conductor plane at a pressure of 50 to 150 bar and a temperature of at least 80 °C and thus laminated, whereby the contact areas of the first conductor plane are caused at least partially to bulge through the holes in the adhesive layer towards the surface of the connecting areas of the second conductor plane so that the surfaces of the connecting areas are at a distance from the surface of the connecting areas of the second conductor plane which is shorter than the thickness of the connecting areas. The second conductor plane with the connecting areas (solder eyes) is then produced from the conductive film, whereby the solder eyes of the second conductor plane border the holes in the adhesive layer, whereupon the pads of the first conductor plane can be electrically connected to the corresponding solder eyes in the second conductor plane by soldering or by the application of a conductive paste.

公开(公告)号：EP0666705A2

公开(公告)日：1995-08-09

申请号：EP95101023.0

申请日：1995-01-26

Applicant: MOLEX INCORPORATED

Inventor： Fuerst, Robert M. ,  Krehbiel, Fred Love ,  Krebaum, Paul

IPC: H05K5/02 ,  H01R13/648

CPC classification number: H05K3/326 ,  H01R4/04 ,  H01R13/7195 ,  H05K1/0215 ,  H05K1/09 ,  H05K1/118 ,  H05K3/306 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/0218 ,  H05K2201/023 ,  H05K2201/091 ,  H05K2201/1003 ,  H05K2201/1059 ,  H05K2203/0425

Abstract: An electrical connector assembly (10) includes a housing (26) fabricated of a first metal material and having at least one integral pin (36) projecting from a face (34) thereof. A flat flexible circuit (20) is mounted against the face of the housing and includes a ground plane (44) on a side thereof facing the housing. The circuit has a hole (40) for receiving the integral pin (36) of the housing. The ground plane (44) is of a second metal material different from that of the housing. An omni-directional conductive adhesive (46) is deposited on the ground plane (44) over the area of the hole to expand the conductive interface between the metal housing (26) and the metal ground plane (44). Preferably, the conductive adhesive (46) includes abrasive grain-like particles.