公开(公告)号：EP1403050B1

公开(公告)日：2006-11-29

申请号：EP03021553.7

申请日：2003-09-24

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Shinkai, Yuji

IPC: B41J2/14 ,  B41J2/16

CPC classification number: H05K3/363 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/20 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y10T29/42 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49401

公开(公告)号：EP0826152B1

公开(公告)日：2006-11-15

申请号：EP96915407.9

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WOOD, Alan, G. ,  FARNWORTH, Warren, M. ,  AKRAM, Salman ,  HEMBREE, David, R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/316 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

公开(公告)号：EP1705972A1

公开(公告)日：2006-09-27

申请号：EP05738530.4

申请日：2005-04-28

Applicant: IBIDEN CO., LTD.

Inventor： KARIYA, Takashi, IBIDEN CO., LTD. ,  FURUTANI, Toshiki, IBIDEN CO., LTD.

IPC: H05K3/46

CPC classification number: H05K1/0271 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49151 ,  Y10T29/49162 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30µm, and the aspect ratio Rasp of external conductor posts 50a, which are positioned at external portions of the low elastic modulus layer 40, is greater than or equal to the aspect ratio Rasp of internal conductor posts 50b, which are positioned at internal portions of the low elastic modulus layer 40.

Abstract translation: 多层印刷线路板10包括：堆积层30，其形成在核心基板20上并具有布置在上表面上的导体图案32; 形成在积层30上的低弹性模量层40; 设置在低弹性模量层40的上表面上并通过焊料凸点66连接到IC芯片70的焊盘52; 以及导体柱50，其穿过低弹性模数层40并且将平台52与导体图案32电连接。导体柱50具有不小于4的纵横比Rasp（高度/最小直径）和最大直径超过30μm， 并且位于低弹性模量层40的外部的外部导体柱50a的纵横比Rasp大于或等于位于低的内部部分的内部导体柱50b的纵横比Rasp 弹性模量层40。

公开(公告)号：EP1691206A2

公开(公告)日：2006-08-16

申请号：EP06075592.3

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wood, Alan G. ,  Farnworth, Warren M. ,  Akram, Salman ,  Hembree, David R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/316 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 一种用于测试未封装的半导体裸片的方法和设备包括母板（10）和安装在母板（10）上并且适于与裸片（14）建立暂时电连接的多个互连（12）。 互连件（12）可以形成有硅衬底（20）和凸起的接触构件（16），用于接触管芯（14）的接合焊盘（22）。 或者，可以用安装在绝缘膜（74）上的微凸块接触构件（16）形成互连（16）。 母板（10）允许为了速度和功能而单独测试每个管芯（14），并且还使用标准的老化炉并行地进行老化测试。 在替代实施例中，使用母板/子板布置来执行测试。 每个子板（82）包括互连（12），允许单独测试裸片（14）的速度和功能。 然后可以将多个子板（82）安装到母板（10）上，以使用标准的老化烘箱进行老化测试。

公开(公告)号：EP1632354A3

公开(公告)日：2006-04-05

申请号：EP05025554.6

申请日：2003-09-24

Applicant: Brother Kogyo Kabushiki Kaisha

Inventor： Shinkai, Yuji Technology Planning & IP Dept.

IPC: B41J2/14 ,  B41J2/16

CPC classification number: H05K3/363 ,  B41J2/14209 ,  B41J2/1609 ,  B41J2/1623 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  B41J2202/20 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y10T29/42 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49401

Abstract: A surface electrode is provided on a surface of a piezoelectric, element for changing the volume of each pressure chamber in an inkjet head. The surface electrode has a main electrode portion opposed to the pressure chamber and a connecting portion not opposed to the pressure chamber. A land is provided on one end of the connecting portion of the surface electrode. The land is electrically connected to the surface electrode. When the land is connected to a terminal of an FPC, a driving signal can be transmitted to the surface electrode. The land is therefore connected to the terminal using solder and a thermosetting resin covering the surface of the solder, or using only a thermosetting resin.

Abstract translation: 喷墨头包括：（a）墨通道单元，其具有限定每个压力室的压力室和壁部; （b）具有压电片，表面电极和焊盘的致动器单元; （c）印刷电路板，其上设置有连接到所述焊盘的端子和预定布线图案; （d）将土地连接至码头的金属债券; 和（e）突出部，设置在连接部上。 喷墨头包括：（a）墨通道单元，其具有限定每个压力室的压力室和壁部; （b）具有设置在墨通道单元上的压电片的致动器单元; （c）压电片（41）上的表面电极（35），具有与压力室相对的主电极部分和与壁部分相对的连接部分，以及在相对的区域中的压电片材上的焊盘（36） 到墙部分; （d）印刷电路板（50），其上设置有连接到所述焊盘的端子（54）和预定的布线图案; （e）将土地连接至码头的金属债券; 和（f）设置在连接部分上的突出部（162）。 焊盘与表面电极连接。 金属结合物设置在陆地和沿陆地和终端之间沿着陆地和码头周边延伸的区域之间。 还包括用于制造喷墨头的独立权利要求：（a）在连接部分上形成突起; （b）在终端与土地之间设置金属联结; 以及（c）按地面和终端，使彼此靠近，将土地与终端相互连接，并在土地和终端之间的区域内设置金属结合区域，以及在陆地上延伸的区域; 沿边界沿岸的终点站。

公开(公告)号：EP1465471A3

公开(公告)日：2005-07-27

申请号：EP04007916.2

申请日：2004-04-01

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tomita, Yoshihiro ,  Nakamura, Tadashi ,  Ishimaru, Yukihiro ,  Sugaya, Yasuhiro ,  Honda, Kazuyoshi ,  Okazaki, Sadayuki

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/117 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2201/0919 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0733 ,  H01L2224/0401

Abstract: A wiring board that allows the high-density connection with a plurality of circuit boards within a limited area, a manufacturing method for the same and electronic equipment using the same are provided. A wiring board 100 includes: a plurality of conductive layers 1A to 1G each including one or more wirings for transmitting signals; and a plurality of insulation layers 2 for insulating the respective conductive layers 1A to 1G. The conductive layers 1A to 1G and the insulation layers 2 are laminated alternately, and each of the plurality of conductive layers 1A to 1G is provided with a terminal 1AT to 1GT at at least one of both ends. The terminals 1AT to 1GT are formed stepwise and separated by the insulation layers 2 in a cross-sectional shape of a lamination structure of the conductive layers 1A to 1G and the insulation layers 2.

Abstract translation: 提供允许在有限区域内与多个电路板进行高密度连接的布线板，其制造方法和使用该布线板的电子设备。 布线板100包括：多个导电层1A至1G，每个导体层包括用于传输信号的一个或多个布线; 以及用于绝缘各导电层1A至1G的多个绝缘层2。 导电层1A至1G和绝缘层2交替层叠，并且多个导电层1A至1G中的每一个在两端中的至少一个处设置有端子1AT至1GT。 端子1AT至1GT以导电层1A至1G和绝缘层2的叠层结构的横截面形状逐级形成并由绝缘层2分隔开。

公开(公告)号：EP1173051A4

公开(公告)日：2005-02-02

申请号：EP00900913

申请日：2000-01-25

Applicant: SONY CHEMICALS CORP

Inventor： KURITA HIDEYUKI ,  TANIGUCHI MASATO

IPC: G02F1/1345 ,  H05K1/14 ,  H05K3/00 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/361 ,  H05K3/305 ,  H05K3/323 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09709 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/0759

Abstract: A flexible printed wiring board (10) in which a metallic bump (1a) of a first flexible printed wiring part (1) is connected to a connection pad (2a) of a second flexible wiring part (2), wherein the first flexible printed wiring part (1) is composed of a conductive layer (4) and an insulating layer (5) adjacent to the conductive layer (4), a hole (A) reaching the conductive layer is made in the insulating layer (5), a metallic plug (6) is formed in the hole (A) by electroplating, and the end of the metallic plug (6) projecting from the insulating layer (5) serves as a metallic bump (1a). As many flexible printed wiring boards as possible are produced from a laminated sheet for a flexible printed wiring having a predetermined size.

公开(公告)号：EP1250033B1

公开(公告)日：2004-09-08

申请号：EP02013314.6

申请日：1997-12-23

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tsukamoto, Masahide

IPC: H05K3/40 ,  H05K3/46 ,  H05K3/20 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/80 ,  H01L23/3107 ,  H01L23/49827 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/115 ,  H05K3/007 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4658 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49345 ,  H01L2924/00

公开(公告)号：EP1163828B1

公开(公告)日：2004-08-11

申请号：EP00906802.4

申请日：2000-01-14

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： BERGSTEDT, Leif ,  LIGANDER, Per ,  GEVORGIAN, Spartak

IPC: H05K3/32 ,  H01P3/08

CPC classification number: H05K1/162 ,  H05K1/0231 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/09318

公开(公告)号：EP1364788A3

公开(公告)日：2004-05-06

申请号：EP02257528.6

申请日：2002-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kim, Jeong-seon ,  Cho, Seo-hyun ,  Son, Dae-woo ,  Kang, Sa-yoon ,  Jung, Myung-song

IPC: B41J2/14 ,  B41J2/16

CPC classification number: H05K3/361 ,  B41J2/14072 ,  H05K1/147 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0397 ,  H05K2203/0195

Abstract: An ink jet print head, a method of bonding a flexible printed circuit (FPC) (60) cable for an ink jet print head, and an apparatus adopting the method are provided. In this bonding method, the bonding portion of an FPC conductor (61) is heated being pressed down on a corresponding pad (20) formed on a substrate (10) for an ink jet print head. Then, at least two pads (20) are bonded at a time. In this bonding method, an electrical defect due to pad peel-off phenomenon, which is created by an conventional tape automated bonding (TAB) method in which the conductors of an FPC cable are bonded to the pads on a substrate in a manner where one conductor is bonded to a pad at a time, is removed to increase the reliability of bonding. In addition, the bonding of a plurality of pads (20) at a time leads to a reduction in the time required for bonding.