公开(公告)号：EP1023743A2

公开(公告)日：2000-08-02

申请号：EP98934369.4

申请日：1998-07-08

Applicant: Dytak Corporation

Inventor： NANIS, Leonard ,  KEUKELAAR, Ronald

IPC: H01L21/00

CPC classification number: G01R1/06761 ,  G01R3/00 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/241 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

Abstract: An improved wear resistant bump contact (Fig. 1, item 16) is produced by the inclusion of small particles (18) of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer (19) of noble, non oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad.

公开(公告)号：EP0826152A4

公开(公告)日：1998-12-23

申请号：EP96915407

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY INC

Inventor： WOOD ALAN G ,  FARNWORTH WARREN M ,  AKRAM SALMAN ,  HEMBREE DAVID R

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  G01R31/02

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：EP0826152A1

公开(公告)日：1998-03-04

申请号：EP96915407.0

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WOOD, Alan, G. ,  FARNWORTH, Warren, M. ,  AKRAM, Salman ,  HEMBREE, David, R.

IPC: G01R31 ,  G01R1 ,  H01L21 ,  H01L23 ,  H05K3 ,  G01R3

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 用于测试未封装半导体晶片的方法和装置包括安装在母板（10）上的母板（10）和多个互连（12），并适于建立与芯片（14）的临时电连接。 互连（12）可以形成有用于接触管芯（14）的接合焊盘（22）的硅衬底（20）和凸起的接触构件（16）。 或者，互连（16）可以形成有安装在绝缘膜（74）上的微凸块接触构件（16）。 母板（10）允许每个模具（14）单独测试速度和功能，并且还可以使用标准老化炉并行测试。 在替代实施例中，使用母板/子板布置进行测试。 每个子板（82）包括允许骰子（14）单独测试速度和功能的互连（12）。 然后可以将多个子板（82）安装到母板（10）上，以使用标准老化烤箱进行老化测试。

公开(公告)号：EP0820217A1

公开(公告)日：1998-01-21

申请号：EP97110015.1

申请日：1997-06-19

Applicant: E.I. DU PONT DE NEMOURS AND COMPANY

Inventor： Felten, John James ,  Padlewski, Stephan

IPC: H05K1/09 ,  H05K3/40 ,  H01B1/22

CPC classification number: H05K1/095 ,  H05K3/246 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2203/0554

Abstract: Electrolytic and electroless processes which use a solid plug of polymer thick film composition to fill throughholes and composition therefor. The composition comprises a trimodal conductive mixture dispersed in an organic vehicle wherein the trimodal conductive mixture consists of particles of spherical silver, flake silver and silver-coated copper.

Abstract translation: 使用聚合物厚膜组合物的固体塞填充通孔及其组成的电解和无电工艺。 组合物包含分散在有机载体中的三峰导电混合物，其中三峰导电混合物由球形银，薄片银和镀银铜的颗粒组成。

公开(公告)号：EP0804061A1

公开(公告)日：1997-10-29

申请号：EP96907729.6

申请日：1996-03-29

Applicant: IBIDEN CO, LTD.

Inventor： YASUE, Toshihiko ,  HIRAMATSU, Yasuji ,  YANO, Hideki ,  ISHITANI, Yoshifumi ,  KAWAMURA, Yoichiro ,  MURASE, Hideki ,  SUZUKI, Ayumi ,  KAWADE, Masato

IPC: H05K3/46

CPC classification number: H05K3/4661 ,  H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer, a lower conductor circuit layer and a resin insulating layer electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an insulating layer made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer for electroless plating made from a heat-resistant resin as an upper layer, and if necessary, a resin is filled in a concave portion created between conductor circuits of the lower layer so as to render the surface into the same plane as the surface of the conductor circuit.

Abstract translation: 提供一种具有优异的分辨率，层间绝缘性能和耐冷热冲击性的多层印刷电路板，而不会在表面上形成不均匀性，并且即使树脂绝缘层的厚度较薄，也降低剥离强度。 本发明提出了一种多层印刷电路板，包括上导体电路层，下导体电路层和电绝缘两个导体电路层的树脂绝缘层，其中树脂绝缘层是由绝缘层构成的复合层， 难以溶于作为下层的酸或氧化剂的耐热树脂和由耐热树脂作为上层制成的用于化学镀的粘合剂层，如果需要，树脂填充在导体 电路，以使表面进入与导体电路的表面相同的平面。

公开(公告)号：EP0784913A2

公开(公告)日：1997-07-23

申请号：EP96923026.0

申请日：1996-07-31

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： VAN LOENEN, Evert, Jan ,  VAN VEEN, Gerardus, Nicolaas, Anne

IPC: H01F41 ,  H02K3 ,  H02K15 ,  H05K1 ,  H05K3

CPC classification number: H05K1/0265 ,  H02K3/26 ,  H05K1/165 ,  H05K3/24 ,  H05K2201/0347 ,  H05K2201/098 ,  H05K2201/09881 ,  Y10S310/06 ,  Y10T29/49155

Abstract: The invention relates to a method of manufacturing a pattern of conductors (10) on a polyimide base (1). After the conductors (11) have been formed in known manner ridges (21) of an insulating material are formed in the metal-free zones by applying, exposing and developing a UV-sensitive resist. Subsequently, metal is deposited on the conductors (11), the ridges (21) preventing short-circuits.

公开(公告)号：EP0708581A2

公开(公告)日：1996-04-24

申请号：EP95307184.2

申请日：1995-10-11

Applicant: AT&T Corp.

Inventor： Evans, Michael D. ,  Law, Henry Hon ,  Kim, Tae Yong ,  Wu, Te-Sung

IPC: H05K3/18 ,  C23C18/16 ,  C23C18/18

CPC classification number: C23C18/1851 ,  C23C18/1608 ,  C23C18/1651 ,  C23C18/1692 ,  C23C18/1865 ,  C23C18/1889 ,  C23C18/32 ,  C23C18/38 ,  C23C18/50 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/167 ,  H05K3/184 ,  H05K3/24 ,  H05K3/38 ,  H05K3/381 ,  H05K2201/0347 ,  H05K2203/0565 ,  H05K2203/1105

Abstract: A process for the metalization of substrates is disclosed. The metal either forms a coating over the entire substrate, or it is patternwise deposited on the substrate surface. Metal is patternwise formed on the substrate either by forming a pattern of resist material on the substrate and depositing the material in the interstices defined by the pattern or by forming a patterned resist layer over a metal layer and transferring the pattern into the substrate using conventional techniques. The patterned resist layer is formed on the substrate using conventional techniques. The substrate is treated with reagents that promote the electroless plating of metal on the substrate surface. If the resist material has been previously formed on the substrate surface, the substrate surface is then dried. The remaining resist is then removed from the substrate surface. The substrate surface is then exposed to an electroless plating bath to form nickel onto those portions of the substrate surface that were treated with the sensitizing and activating solutions. The substrate is then heated to at least 180°C. Additional layers of metal are formed on the substrate. After the additional layers are so formed, the substrate is again heated to a temperature of at least about 180°C after each layer is so formed.

公开(公告)号：EP0685099A1

公开(公告)日：1995-12-06

申请号：EP95902243.0

申请日：1994-12-16

Applicant: PHILIPS ELECTRONICS N.V.

Inventor： HERMENS, Hendrik, Christiaan, Maria ,  JACOBS, Lucas, Adrianus, Gertruda ,  DRIESSEN, Henrikus, Christian, Maria, Peter ,  VAN DER HORST, Cornelis, Hubertus, Theresia ,  SCHÄFER, Hubertus, Elisabeth, Antoon

IPC: G09F9 ,  G02F1 ,  H01R12 ,  H05K3

CPC classification number: G02F1/13452 ,  H01R12/7076 ,  H05K3/24 ,  H05K2201/0326 ,  H05K2201/0347

Abstract: A picture display device comprises two supporting plates (1, 2) which enclose an electro-optical layer (5). One of the two supporting plates (1) is provided with a plurality of at least substantially transparent picture electrodes (74), while the other supporting plate (2) comprises at least one counter electrode (9). The picture electrodes (74) are connected to respective contact faces (12) by means of at least substantially transparent conductor tracks (11), on which contact faces a semiconductor driving device (13) is arranged. Outside the area of the electro-optical layer (5) at least the ends of the conductor tracks (11) are provided with a metallic top coating (17) which extends to the proximity of the associated contact face (12). To suppress resistance variations in the conductor tracks with respect to each other and from device to device, the metallic top coating (17) continues in the direction of the contact face (12) in a form (of, for example, a relatively narrow metal track (18)) which extends across the contact face (12) but covers only a part thereof. To manufacture such a picture display device by means of the method according to the invention, a deposition mask (25) is provided on the conductor tracks, which mask leaves clear a comb-shaped pattern (23) having teeth (24) which are narrower than the conductor tracks. At least one of the teeth (24) extends at the location of an end of the conductor track (11) and an associated contact face (12). While masking the deposition mask (25), metal is selectively deposited on the conductor track.

公开(公告)号：EP0657932A2

公开(公告)日：1995-06-14

申请号：EP94119486.2

申请日：1994-12-09

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Tomura, Yoshihiro ,  Bessho, Yoshihiro ,  Hakotani, Yasuhiko

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/181 ,  H05K3/243 ,  H05K3/321 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10568 ,  H05K2201/10719 ,  H05K2201/10984 ,  H05K2203/0577 ,  H05K2203/167 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.

Abstract translation: 根据本发明的芯片载体包括：载体，其包括上表面，下表面和内导体; 以及形成在所述载体主体的上表面上的多个端子电极，所述多个端子电极将LSI芯片电连接到所述内部导体。 用于将电路基板上的多个电极电连接到内部导体的多个凹部设置在载体主体的下表面上，凹部电连接到内部导体。

公开(公告)号：EP0626714A1

公开(公告)日：1994-11-30

申请号：EP94850094.7

申请日：1994-05-27

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON

Inventor： Löf, Stefan

IPC: H01H85/046 ,  H05K1/16

CPC classification number: H05K1/0293 ,  H01H69/022 ,  H01H85/046 ,  H05K1/0209 ,  H05K1/167 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10181 ,  Y10T29/49107

Abstract: In order to reduce the costs of assembled printed circuit boards, a printed board fuse (1) has been developed, which functions with great reliability at low manufacturing costs. By coating a large area of a printed board with metal, for example, by plating, a well-defined thickness of a metal layer (9) may be achieved in which a fuse (3) has been separated. The well-defined thickness also allows well-defined geometry of the fuse cross-sectional area and fuse length to be achieved and therefore its resistance and interruption characteristics will also be very accurately defined. In case of a temperature rise, the metal layer (9) surrounding the fuse (3) will have a heat dissipating effect on the fuse, implying an essentially reduced risk of board fire.

Abstract translation: 为了减少组装的印刷电路板的成本，一个印刷电路板的保险丝（1）已经被开发，其与在低的制造成本很高的可靠性的功能。 通过涂敷的印刷电路板的大面积与金属，例如，通过电镀，明确定义的金属层（9）的厚度可以实现，其中一个保险丝（3）已被分离。 该明确定义的厚度，从而允许熔断器横截面积和熔丝长度的良好限定的几何形状来实现，因此，其电阻和中断特性，以便将定义非常精确地设定。 在温度上升的情况下，围绕所述保险丝（3）的金属层（9）将具有在熔丝散热效果，在本质上减少了板火灾风险暗示。