公开(公告)号：EP1097616A1

公开(公告)日：2001-05-09

申请号：EP99931234.1

申请日：1999-07-01

Applicant: Siemens S.A.

Inventor： VAN PUYMBROECK, Jozef

IPC: H05K3/06 ,  H05K1/02

CPC classification number: H05K1/0265 ,  H05K3/0032 ,  H05K3/0082 ,  H05K3/027 ,  H05K3/062 ,  H05K3/064 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0305 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2203/0505

Abstract: The rough conducting structures (GL) and the fine conducting structures (FL) are etched out of a metal layer in a common etching process, whereby an etch resist structured by means of photolithography is used in the area containing the rough conducting structures (GL) and an etch resist structured by means of a laser beam is used in the area containing the fine conducting structures.

公开(公告)号：EP1083779A1

公开(公告)日：2001-03-14

申请号：EP99919584.5

申请日：1999-05-13

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro, Ogaki-kita-kojou, Ibiden K. K. ,  KARIYA, Takashi, Ogaki-kita-kojou, Ibiden K. K. ,  MORI, Yoji, Ogaki-kita-kojou, Ibiden K. K.

IPC: H05K3/46 ,  H05K1/02 ,  H05K3/18

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，在构成拐角部分C等于或小于90度的部分上加入一个纸条F，并形成布线图案58。 由于添加了文件F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于没有集中到交叉部分X的应力，布线图案中不会导致断开，也没有气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性。

公开(公告)号：EP1046326A1

公开(公告)日：2000-10-25

申请号：EP98960572.0

申请日：1998-11-30

Applicant: LITTELFUSE, INC.

Inventor： KRUEGER, David, J. ,  NEUHALFEN, Andrew, J.

IPC: H05K1/16 ,  H01H69/02

CPC classification number: H01H85/046 ,  H01H69/022 ,  H05K1/0293 ,  H05K2201/0305 ,  H05K2201/0338 ,  H05K2201/09727 ,  H05K2201/10181

Abstract: A printed circuit board assembly (10) comprising a printed circuit board having a plurality of conductive traces (25, 30) deposited on a surface thereof to define a plurality of electrical circuit geometries. A plurality of thin film fuses (35) are deposited on the printed circuit board, each fuse providing circuit protection to one of the plurality of conductive traces.

公开(公告)号：EP1029431A1

公开(公告)日：2000-08-23

申请号：EP98943307.3

申请日：1998-08-20

Applicant: INTEL CORPORATION

Inventor： LEDDIGE, Michael ,  SPRIETSMA, John

IPC: H05K7/02

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09727

Abstract: A connector (400) for coupling high frequency signals between devices includes a substrate having an array of vias (410) for coupling a reference voltage to reference voltages traces (460) that extend along the substrate surface between the devices. Signal traces (430) including device pads (434) for coupling signals to and from the devices alternate with the reference voltage traces (460). The widths of the reference voltage traces (460) are varied to maintain a substantially constant separation between the reference voltage trace (460) and an adjacent signal trace (430).

Abstract translation: 用于在器件之间耦合高频信号的连接器（400）包括具有用于将参考电压耦合到在器件之间沿着衬底表面延伸的参考电压迹线（460）的衬底阵列的衬底（410）。 包括用于耦合去往和来自装置的信号的装置垫（434）的信号迹线（430）与参考电压迹线（460）交替。 参考电压迹线（460）的宽度被改变以维持参考电压迹线（460）与相邻信号迹线（430）之间的基本上恒定的间隔。

公开(公告)号：EP0883173A1

公开(公告)日：1998-12-09

申请号：EP96930376.7

申请日：1996-09-12

Applicant: Ibiden Co., Ltd.

Inventor： ASAI, Motoo ,  KAWAMURA, Yoichiro ,  MORI, Yoji

IPC: H01L23/12 ,  H05K1/03

CPC classification number: H01L23/49833 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R12/523 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/114 ,  H05K3/184 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0212 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2201/10734

Abstract: A board for mounting electronic circuit parts includes a first connection terminal group including a plurality of connection terminals densely formed on the top surface of a substrate having through holes formed therein, and a second connection terminal group including a plurality of connection terminals formed at at least the peripheral portion of a back surface of the substrate. The first connection terminal group is connected to the second connection terminal group by way of the through holes. A build-up multilayer interconnection layer having via holes is formed on the top surface of the substrate, so that the first connection terminal group is connected to the second connection terminal group through the build-up multilayer interconnection layer and the through holes. According to another aspect, each signal line on the top surface of the build-up multilayer interconnection layer comprises a plurality of wiring patterns having different widths and a taper-shaped pattern that connects those wiring patterns together and whose width continuously changes. Each signal line has a smaller width at an area having a relatively high wiring density than at an area having a relatively low wiring density.

Abstract translation: 用于安装电子电路部件的板包括：第一连接端子组，包括密实地形成在其上形成有通孔的基板的顶表面上的多个连接端子，以及包括至少形成有多个连接端子的第二连接端子组 衬底的背面的周边部分。 第一连接端子组通过通孔连接到第二连接端子组。 在基板的顶面形成有具有通孔的积层多层互连层，使得第一连接端子组通过积层多层互连层和通孔与第二连接端子组连接。 根据另一方面，积层多层互连层的顶表面上的每个信号线包括具有不同宽度的多个布线图案和将这些布线图案连接在一起并且其宽度连续变化的锥形图案。 每个信号线在具有比布线密度相对较低的区域具有相对高的布线密度的区域上具有较小的宽度。

公开(公告)号：EP0626714B1

公开(公告)日：1997-03-26

申请号：EP94850094.7

申请日：1994-05-27

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON

Inventor： Löf, Stefan

IPC: H01H85/046 ,  H05K1/16

CPC classification number: H05K1/0293 ,  H01H69/022 ,  H01H85/046 ,  H05K1/0209 ,  H05K1/167 ,  H05K2201/0347 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10181 ,  Y10T29/49107

公开(公告)号：EP0414546A3

公开(公告)日：1991-11-06

申请号：EP90309266.6

申请日：1990-08-23

Applicant: NCR International, Inc.

Inventor： Alexander, Arthur Ray ,  Rostek, Paul Michael

IPC: G06F13/40 ,  H05K1/00

CPC classification number: G06F13/40 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/0298 ,  H05K9/0039 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09327 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: A printed circuit board backpanel (100) uses strip-line construction to allow emitter coupled logic (ECL) signals and transistor-transistor logic (TTL) signals on the same signal layer, while providing electromagnetic interference (EMI) emission control. Disposed between ground layers (102,130), and separated bydielectric layers (104, 108, 112, 116, 120, 124, 128), are arranged signal layers (106, 114, 118, 126) and power layers (110, 122).

公开(公告)号：EP0448614A1

公开(公告)日：1991-10-02

申请号：EP90900866.0

申请日：1989-12-12

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： KAPPEL, Andreas

IPC: B41J2 ,  H05K1

CPC classification number: H05K1/0265 ,  B41J2/14072 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2202/11 ,  H05K2201/0784 ,  H05K2201/09727

Abstract: Grâce à un dimensionnement approprié d'une structure de transition (ÜV) d'une configuration de tracés conducteurs prévue sur un substrat à couche mince (DS), reliant les tracés conducteurs étroitement écartés entre eux (LA) dans la zone des éléments de chauffage (RH) aux tracés conducteurs ayant un large écart entre eux (LB) dans la zone des contacts de liaison, on obtient une résistance d'amenée des tracés conducteurs (Li) qui est la plus uniforme possible, tout en demeurant aussi faible que possible pour tous les éléments de chauffage (RH). A cet effet, il est stipulé une prescription de dimensionnement qui, pour des grandeurs d'entrée prédéterminées, à savoir, les largeurs des tracés conducteurs (da, db) et les largeurs de fente (Sa, Sb) dans les deux zones et la largeur de fente (Sv) de la structure de transition (ÜV), fournit, comme grandeurs de sortie, la largeur des conducteurs (dv) dans la structure de transition (ÜV).

公开(公告)号：EP0143493B1

公开(公告)日：1991-06-19

申请号：EP84201675.0

申请日：1984-11-20

Applicant: Centralab Inc.

Inventor： Hilgers, John Louis

IPC: H03H1/00 ,  H01C17/22

CPC classification number: H03F3/45475 ,  H01H85/046 ,  H01L23/5256 ,  H01L2924/0002 ,  H03F2203/45522 ,  H03G1/0088 ,  H03H7/24 ,  H05K1/0293 ,  H05K1/092 ,  H05K3/28 ,  H05K2201/09727 ,  H05K2201/10181 ,  H01L2924/00

公开(公告)号：EP0307597A1

公开(公告)日：1989-03-22

申请号：EP88112310.3

申请日：1988-07-29

Applicant: MICROSET S.R.L.

Inventor： Bellini, Mario

IPC: H05K1/00 ,  G06F13/40

CPC classification number: H05K1/0219 ,  H05K3/42 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09727

Abstract: In the printed circuit mother board (1) for busses of microprocessors each track (4) of the printed circuit is separated from the adjacent one by a ground track (5) permitting the signals flowing in the printed circuit tracks (4) to be insulated from each other and this both on the component side (2) and the welding side (3) of the mother board (1). The ground tracks (5) are connected to each other by ground bridges (6).

Abstract translation: 在用于微处理器总线的印刷电路母板（1）中，印刷电路的每个轨迹（4）通过接地轨道（5）与相邻的轨迹（4）分离，允许在印刷电路轨道（4）中流动的信号被绝缘 （2）和母板（1）的焊接侧（3）彼此相对。 地面轨道（5）通过地面桥梁（6）相互连接。