公开(公告)号：EP1995053B1

公开(公告)日：2013-05-01

申请号：EP07714348.5

申请日：2007-02-16

Applicant: Daicel Chemical Industries, Ltd.

Inventor： SHIMIZU, Kiyoshi ,  YAMATO, Yo

IPC: B32B5/18 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/036 ,  B32B5/18 ,  B32B15/08 ,  H05K1/0366 ,  H05K1/0393 ,  H05K3/12 ,  H05K3/185 ,  H05K2201/0116 ,  Y10T29/49155 ,  Y10T428/24331 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/249979

公开(公告)号：EP2413674A3

公开(公告)日：2012-10-03

申请号：EP11164848.1

申请日：2011-05-04

Applicant: Nitto Denko Corporation

Inventor： Hasegawa, Mineyoshi ,  Okumura, Keisuke ,  Inoue, Shinichi ,  Hanazono, Hiroyuki

IPC: H05K1/03 ,  C08J5/18 ,  C08L27/12 ,  H01B3/44 ,  H01M8/10

CPC classification number: H05K1/034 ,  H01B3/445 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/0116 ,  H05K2201/015

Abstract: A plurality of conductor traces (2) are formed on a porous base insulating layer (1) made of porous ePTFE (expanded polytetrafluoroethylene). Each conductor trace has a laminated structure of a seed layer and a conductor layer. A cover insulating layer (3) is formed on the base insulating layer to cover each conductor trace. The ePTFE used as the porous base insulating layer has continuous pores. An average pore size of the ePTFE is not less than 0.05 µm and not more than 1.0 µm.

Abstract translation: 在由多孔ePTFE（膨胀聚四氟乙烯）制成的多孔基底绝缘层（1）上形成多个导体迹线（2）。 每个导体迹线具有种子层和导体层的层叠结构。 覆盖绝缘层（3）形成在基底绝缘层上以覆盖每个导体迹线。 用作多孔基底绝缘层的ePTFE具有连续的孔隙。 ePTFE的平均孔径不小于0.05μm且不大于1.0μm。

公开(公告)号：EP2026379B1

公开(公告)日：2012-08-15

申请号：EP07743957.8

申请日：2007-05-23

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： NOMIYA, Masato c/o Murata Manufacturing Co., Ltd ,  SAKAI, Norio c/o Murata Manufacturing Co., Ltd ,  NISHIDE, Mitsuyoshi c/o Murata Manufacturing Co., Ltd

IPC: H01L23/15 ,  H01L23/13 ,  H01L21/48

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K3/305 ,  H05K3/4626 ,  H05K3/4629 ,  H05K2201/0116 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1147 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: Provided is a method for manufacturing a multilayer ceramic electronic component, by which an underfill resin for fixing a surface mounting electronic component is prevented from flowing out, and the component can be mounted at a high density and a high accuracy. The highly reliable multilayer ceramic electronic component, which is manufactured by such manufacturing method and has excellent shock resistance and well applicable to miniaturization, is also provided. On a base section (11), which is to be mounted with a surface mounting electronic component (13), such as a semiconductor element, and has a nonmetal inorganic powder as a main component, a resin introducing section (11A) positioned outside of a vertical projection region (R) of the surface mounting electronic component is mounted. The resin introducing section is supplied with a resin (22), and the base section and a gap between the base section and a multilayer ceramic element (4) are filled with the resin. An unsintered ceramic base material layer (first ceramic layer (1)) and a shrinkage suppressing layer (second ceramic layer (2)) for suppressing shrinkage of the unsintered ceramic base material layer in the planar direction are stacked, and an unfired multilayer ceramic base element which does not shrink in a direction orthogonally intersecting with the stacking direction in a firing step is formed.

Abstract translation: 一种制造多层陶瓷电子器件的方法，其中不会发生用于固定表面贴装电子器件的底部填充树脂的泄漏，并且可以进行器件的高密度，高精度的安装，以及高可靠性的多层陶瓷电子器件 ，其通过上述制造方法制造并且具有优异的耐冲击性和与小型化的良好兼容性。 位于表面安装电子设备13的垂直投影区域R外侧的树脂引入部分11A设置在座
部11上，该座部11包含非金属无机粉末作为主要部件，表面安装电子器件例如半导体元件 ，并且树脂22被供应到树脂引入部分以便将树脂填充到座椅部分中以及座部分和多层陶瓷元件组件4之间的间隙。未烧结的陶瓷基材料层（第一陶瓷层1 ）和用于限制未烧结的陶瓷基材层在平面方向上的收缩的收缩限制层（第二陶瓷层2），从而形成未烧结的多层陶瓷元件组件，其在与 烧成工序中的层叠方向。

公开(公告)号：EP2025210B1

公开(公告)日：2012-02-22

申请号：EP07718465.3

申请日：2007-05-25

Applicant: A.B. Mikroelektronik Gesellschaft mit beschränkter Haftung

Inventor： HAEGELE, Bernd

IPC: H05K1/05 ,  H05K3/28 ,  H05K3/44 ,  C03C3/064 ,  C23C4/18

CPC classification number: H05K1/053 ,  C03C3/064 ,  C23C4/18 ,  H05K1/092 ,  H05K2201/0116 ,  H05K2201/017 ,  H05K2201/0179 ,  H05K2203/1147 ,  H05K2203/1366 ,  Y10T29/49126 ,  Y10T29/49146

Abstract: Circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the latter having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

公开(公告)号：EP1265468B1

公开(公告)日：2011-12-28

申请号：EP02253907.6

申请日：2002-06-05

Applicant: Kabushiki Kaisha Toshiba

Inventor： Asakawa, Koji, c/o Intellectual Property Division ,  Hotta, Yasuyuki, Intellectual Property Divison ,  Matake, Shigeru, Intellectual Property Division ,  Hiraoka, Toshiro, c/o Intellectual Property Div.

IPC: H05K3/10 ,  H05K3/18 ,  H05K3/40

CPC classification number: H05K3/10 ,  H05K1/034 ,  H05K3/0002 ,  H05K3/0082 ,  H05K3/107 ,  H05K3/185 ,  H05K3/422 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2203/056 ,  H05K2203/107 ,  H05K2203/1147 ,  Y10T29/49155 ,  Y10T29/49215

公开(公告)号：EP1910852A4

公开(公告)日：2011-10-26

申请号：EP06788901

申请日：2006-07-28

Applicant: FOSTER MILLER INC

Inventor： FARRELL BRIAN ,  GANNON JOHN J ,  CAMPBELL THOMAS G ,  COPPOLA PAT ANTHONY ,  O'REILLY SEAN GERALD ,  BURKE JOSEPH F

IPC: H01L23/02 ,  H01Q1/28

CPC classification number: H01Q1/286 ,  B64D43/00 ,  H01Q21/065 ,  H05K1/00 ,  H05K1/038 ,  H05K1/147 ,  H05K3/0058 ,  H05K3/0064 ,  H05K3/3447 ,  H05K3/36 ,  H05K3/4046 ,  H05K2201/0116 ,  H05K2201/0281 ,  H05K2201/029 ,  H05K2201/10303

公开(公告)号：EP1912286A4

公开(公告)日：2011-04-06

申请号：EP06757212

申请日：2006-06-09

Applicant: SUMITOMO ELECTRIC INDUSTRIES

Inventor： IDOMOTO YUICHI ,  OKUDA YASUHIRO

IPC: H01R11/01 ,  H01R43/00 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/119 ,  H01R12/7076 ,  H05K3/0058 ,  H05K3/368 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09045 ,  H05K2201/09845 ,  H05K2201/10378 ,  H05K2201/2018 ,  Y10T428/24802

公开(公告)号：EP2211295A3

公开(公告)日：2011-01-19

申请号：EP10000633.7

申请日：2010-01-22

Applicant: Phytrex Technology Corporation

Inventor： Hsiao, Feng-Chi ,  Yang, Kun-Shan ,  Lin, Tung-Fu ,  Cheng, Chin-Fen ,  Lee, Chih-Wei

IPC: G06K19/077 ,  H05K1/00 ,  H04M1/02 ,  H04B1/38

CPC classification number: G06K19/077 ,  G06K19/041 ,  G06K19/07739 ,  G06K19/07743 ,  G06K19/07749 ,  G06K19/07769 ,  H04B1/3816 ,  H05K1/028 ,  H05K1/0281 ,  H05K3/0064 ,  H05K2201/0116 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/10037

Abstract: The present invention provides a signal processing device comprising: a first substrate (11), one side surface thereof (20) being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact, there being an electrical connection between the first and third contacts; a second substrate (10), one side surface thereof being provided with at least an integrated circuit (102) or an antenna (13); and a first connecting portion (12) for connecting the first and second substrates; wherein the second and fourth contacts are electrically connected to the integrated circuit or antenna via the first connecting portion.

公开(公告)号：EP1738627A4

公开(公告)日：2010-05-05

申请号：EP05723085

申请日：2005-02-15

Applicant: MOTOROLA INC

Inventor： GALL THOMAS P ,  PFEIFER MICHAEL ,  POLAK ANTHONY ,  POMEROY MICHAEL J

IPC: H05K1/02 ,  H05K3/42 ,  H05K5/00 ,  H05K5/02 ,  H05K7/20

CPC classification number: H05K5/0047 ,  H05K1/0215 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/42 ,  H05K5/0213 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2201/0999 ,  H05K2201/10666 ,  H05K2203/0191 ,  H05K2203/1178 ,  H05K2203/1394

公开(公告)号：EP2051850B1

公开(公告)日：2009-11-18

申请号：EP07814146.2

申请日：2007-08-16

Applicant: Honeywell International, Inc.

Inventor： JACKSON, Merrill M. ,  HUMPHREY, David

IPC: B32B5/18 ,  B32B15/08 ,  B32B33/00 ,  C09D5/00

CPC classification number: C23C26/00 ,  C23C28/00 ,  C25D5/48 ,  C25D7/00 ,  H05K3/244 ,  H05K3/28 ,  H05K2201/0116 ,  H05K2201/0769 ,  H05K2203/086 ,  H05K2203/087

Abstract: An electrical component includes a conductive substrate (10), a tin layer (12) formed on the substrate, and a conformal coating (14) formed on the tin layer to impede tin whisker growth. The conformal coating comprises a polymer matrix (15) having gas-filled voids (16) dispersed therethrough. In a method for impeding tin whisker growth from a tin plating or finish formed over an electrical component, a gas is infused (30) into a liquid polymer. The tin plating or finish is then covered (32) with a conformal coating comprising the liquid polymer. Then, one or more of the temperature and pressure of the conformal coating are adjusted (34) to thereby create a dispersion of gas-filled voids comprising the gas in the conformal coating. .

Abstract translation: 电气部件包括导电基板（10），在基板上形成的锡层（12）以及在锡层上形成的共形涂层（14），以阻止锡晶须生长。 保形涂层包含具有分散在其中的充气空隙（16）的聚合物基体（15）。 在用于阻止锡电镀或在电部件上形成的饰面上生长锡晶须的方法中，将气体注入（30）成液态聚合物。 然后用包含液体聚合物的保形涂层覆盖（32）镀锡或涂饰。 然后，调整保形涂层的一个或多个温度和压力（34），从而在保形涂层中产生包含气体的充气空隙的分散体。 。