公开(公告)号：EP1118119A1

公开(公告)日：2001-07-25

申请号：EP99904023.1

申请日：1999-01-15

Applicant: MINNESOTA MINING AND MANUFACTURING COMPANY

Inventor： CLATANOFF, William J. ,  SCHUBERT, Robert J. ,  SCHUELLER, Gayle R. T. ,  SAITO, Yusuki ,  YAMAZAKI, Hideo ,  YASUI, Hideaki

IPC: H01L23/498

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/10681 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A circuit includes a substrate having a dielectric layer with a first surface and a second surface. A conductive layer is formed on the first surface. A beveled via is formed in a dielectric layer of the substrate. The via has a first opening of a first width in the first surface, and a second opening of a second width in the second surface, the second width being greater than the first width. A conductive plug is connected to the conductive layer. The plug is formed in the via and extends from adjacent the first opening toward the second opening, and terminates adjacent the second opening at a plug interface surface. A conductive solder ball is connected to the plug interface surface and extends to protrude from the second surface.

公开(公告)号：EP1102525A1

公开(公告)日：2001-05-23

申请号：EP99929729.4

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： TSUKADA, Kiyotaka, Ibiden Co., Ltd. ,  TAKADA, Masaru, Ibiden Co., Ltd. ,  CHIHARA, Kenji, Ibiden Co., Ltd.

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser is provided. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.

Abstract translation: 提供一种印刷电路板及其制造方法，其在形成具有激光的盲孔时有利于形成上表面图案并防止下表面金属箔被损坏。 绝缘基板（5）的下表面和上表面分别涂覆有下表面金属箔（220）和上表面金属箔（210），其厚度小于下表面金属箔的厚度 （220）。 接下来，在上表面金属箔的与绝缘基板的盲通孔形成部（35）对应的位置形成开口（213）。 通过开口（213）向盲通孔形成部分（35）发射激光（8），形成其底部为下表面金属箔的盲通孔（3）。 然后，将金属镀膜（23）施加到盲孔（3）的壁上，通过蚀刻形成上表面图案（21）和下表面图案（22）。

公开(公告)号：EP1099254A1

公开(公告)日：2001-05-16

申请号：EP99957214.2

申请日：1999-06-16

Applicant: SCHLUMBERGER Systèmes

Inventor： FLETOUT, Christophe ,  THEVENOT, Benoît

IPC: H01L23/498 ,  H01L23/538 ,  G06K19/077

CPC classification number: H05K3/321 ,  H01L23/49855 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2201/10477 ,  H05K2201/10719 ,  H05K2201/10727 ,  H01L2924/00014

Abstract: The invention concerns an integrated circuit module (1) comprising a support film (2) having a first surface (2.1) bearing the integrated circuit (3) and internal connection pads (4) and a second surface (2.2) bearing external connection pads (5) the internal and external connection pads being connected to the integrated circuit, the film support (2) second surface (2.2) comprising at least an electrically insulated peripheral zone (8) of the integrated circuit extending opposite at least one of the internal connection pads (4). The invention also concerns a mixed connection card comprising such a module.

公开(公告)号：EP1083778A1

公开(公告)日：2001-03-14

申请号：EP00116763.4

申请日：2000-08-03

Applicant: Endress + Hauser GmbH + Co.

Inventor： Birgel, Dietmar ,  Hauptvogel, Karl-Peter

IPC: H05K1/11 ,  H05K3/34 ,  H05K3/32

CPC classification number: H05K3/3421 ,  H05K1/036 ,  H05K1/112 ,  H05K3/321 ,  H05K2201/09472 ,  H05K2201/09509 ,  Y02P70/613

Abstract: Die Erfindung betrifft ein Verfahren zum Bestücken einer Leiterplatte (1), auf der zumindest eine Leiterbahn (2, 3) angeordnet ist, mit einem elektronischen Bauteil (4), das zumindest zwei Kontaktierungen (5) aufweist, wobei in die Leiterplatte (1) Sacklochbohrungen (6) eingebracht werden, wobei die Innenflächen der Sacklochbohrungen (6) mit einer leitfähigen Beschichtung (7) versehen werden, wobei die Kontaktierungen (4) in die Sacklochbohrungen (6) eingebracht werden und wobei die Kontaktierungen (4) mit den Sacklochbohrungen (6) leitend verbunden werden.

Abstract translation: 组件安装方法具有导电涂层（7），例如 的Au，在将电子部件接触线（5）插入盲孔中之前，施加到设置在印刷电路板（1）的表面中的盲孔（6）的内壁，用于连接到导电涂层通孔 焊料（8），使用回流焊接技术。

公开(公告)号：EP0971570A1

公开(公告)日：2000-01-12

申请号：EP98901002.0

申请日：1998-01-23

Applicant: IBIDEN CO., LTD.

Inventor： TAKADA, Masaru, Ibiden Co., Ltd. ,  TSUKADA, Kiyotaka, Ibiden Co., Ltd. ,  KOBAYASHI, Hiroyuki ,  MINOURA, Hisashi ,  UKAI, Yoshikazu ,  KONDO, Mitsuhiro

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101∼103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract translation: 在制造包括布置在绝缘层101〜103之间的内层导体电路161,131和从绝缘层的最外表面朝向内层导体电路形成的盲通孔141,142的印刷线路板时，开孔160是 预先形成在位于盲通孔141底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。之后， 在内层导体电路13,161和盲通孔141,142的表面上形成金属镀膜。

公开(公告)号：EP0926720A3

公开(公告)日：2000-01-12

申请号：EP98310284.9

申请日：1998-12-15

Applicant: SHINKO ELECTRIC INDUSTRIES CO. LTD.

Inventor： Hayashi, Mamoru, c/o Shinko Elec. Ind. Co., Ltd. ,  Uchida, Hirofumi, c/o Shinko Elec. Ind. Co., Ltd. ,  Sato, Kiyokazu, c/o Shinko Elec. Ind. Co., Ltd. ,  Miyajima, Yoshinori, Shinko Elec. Ind. Co., Ltd.

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L23/4985 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16237 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0393 ,  H05K1/112 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09827 ,  H05K2203/0195 ,  H05K2203/041 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: There is provided a tape carrier in which the degree of freedom of a fine wiring pattern is enhanced by reducing the diameter A of a via pad so that the pitch of the wiring pattern can be made fine, and a metallic ball (10) can be positively joined to the via pad when the diameter of the metallic ball (10) is as large as possible. A tape carrier comprises: a metallic wiring (3) formed on one side of a tape base material (1) through an adhesive layer (2); and a plurality of via holes (4) formed on the other side of the tape base material (1), via pads (3b) of the metallic wiring (3) being exposed to the plurality of via holes (4). Internal wall surfaces of the via holes, which have been formed by punching the tape material (5), from one side on which the adhesive layer (2) is formed, are subjected to coining-press from the other side of the tape base material (1), so that the via holes (4) are formed into tapered holes (7), the diameters of the open portions (6) which receive the metallic balls (10) are larger than the via pads (3b).

Abstract translation: 提供了一种带式载体，其中通过减小通孔焊盘的直径A来增强精细布线图案的自由度，使得布线图案的间距可以做得很细，金属球（10）可以是 当金属球（10）的直径尽可能大时，它们正好连接到通孔垫。 带状载体包括：通过粘合层（2）形成在带基材（1）的一侧上的金属布线（3）; 以及通过暴露于多个通孔（4）的金属布线（3）的焊盘（3b）形成在带基材（1）的另一侧上的多个通孔（4）。 通过从形成有粘合剂层（2）的一侧冲压带材（5）形成的通孔的内壁表面从带基材的另一侧进行压印 （1），使得通孔（4）形成为锥形孔（7），容纳金属球（10）的开口部（6）的直径大于通孔垫（3b）。

公开(公告)号：EP0823833A3

公开(公告)日：1999-04-14

申请号：EP97112872.3

申请日：1997-07-25

Applicant: IBIDEN CO, LTD.

Inventor： Asai, Motoo

IPC: H05K3/46

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0338

Abstract: A multilayer printed circuit board comprises a core substrate, multilayer wiring layers formed thereon and a solder pad group formed by two-dimensionally arranging pads provided with solder bumps on the surface of the multilayer wiring layer, in which the solder pads of the solder pad group are arranged in only a peripheral portion other than a central portion to form a frame shape and the solder pads located at the outside part among the frame-shaped solder pad group are constructed with flat pads each connected to conductor pattern on their surface and solder bumps formed on the surfaces of the flat pads, while the solder pads located at the inside part are constructed with viaholes each connected to an innerlayer flat pad group located in an innerlayer and solder bumps formed in recess portions of these viaholes.

公开(公告)号：EP0776150A4

公开(公告)日：1999-03-31

申请号：EP96916328

申请日：1996-06-06

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  KAWADE MASATO ,  HIRATUKA SHINJI

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/34 ,  H05K3/46 ,  H05K3/28

CPC classification number: H05K3/3457 ,  H05K1/112 ,  H05K3/184 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0588

Abstract: A printed wiring board suitable for reliable connections and reliable high-density mounting of components by using solder bumps. The printed wiring board has a mounting surface on which are formed pads coated with solder resist and having solder bumps. The position of the solder bump is coincident with the position of a via-hole, or the size of an opening disposed in the solder resist is made greater than a land diameter of the via-hole so that the solder resist does not overlap with the via-hole.

公开(公告)号：EP0844809A2

公开(公告)日：1998-05-27

申请号：EP97116093.2

申请日：1997-09-16

Applicant: IBIDEN CO, LTD.

Inventor： Ono, Yoshitaka ,  Goto, Akihiko ,  Niki, Ayao ,  Asai, Motoo

IPC: H05K3/28 ,  H05K3/38 ,  H05K3/40 ,  G03F7/038

CPC classification number: H05K3/244 ,  G03F7/032 ,  G03F7/0388 ,  H05K1/112 ,  H05K3/184 ,  H05K3/28 ,  H05K3/287 ,  H05K3/3457 ,  H05K3/384 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/0307 ,  H05K2203/0392 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A solder resist composition comprises an acrylate of novolac type epoxy resin and an imidazole curing agent and has a viscosity of 0.5-10 Ps·s adjusted with glycol ether type solvent. A printed circuit board is formed by using such a solder resist composition.

Abstract translation: 阻焊剂组合物包含酚醛清漆型环氧树脂的丙烯酸酯和咪唑固化剂，并且用乙二醇醚型溶剂调节粘度为0.5-10Ps. 通过使用这种阻焊剂组合物形成印刷电路板。

公开(公告)号：EP0658960A3

公开(公告)日：1997-01-29

申请号：EP94119849.1

申请日：1994-12-15

Applicant: Hughes Aircraft Company

Inventor： Sobhani, Mohi

IPC: H01R23/72

CPC classification number: H01R12/52 ,  H01R12/62 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49204

Abstract: Electronic interconnection of two printed wiring structures. Two printed wiring boards (11, 16) or a flexprint circuit (20) and a printed wiring board (11) are interconnected by creating a plated hole pattern (12) on a surface (12) of the printed wiring board (11), and wherein holes (13) of the pattern (12) have a concave cross section. The holes (13) of the plated hole pattern (12) are mated with corresponding bumps (17) or dimples (17) disposed on the second printed wiring board (16) or the flexprint circuit (20). The holes (13) formed in the first printed wiring board (11) are disposed a predetermined depth below a surface (18) of the printed wiring board (11), typically to a depth of between 0.007 inches and 0.020 inches below the surface. The plurality of plated holes (13) are formed by electroless plating or electroplating of the holes (13). The present interconnection structure (10) provides for reliable and self aligning interconnection of the two printed wiring boards (11, 16) or the flexprint circuit (20) and printed wiring board (11).