公开(公告)号：EP2738798A4

公开(公告)日：2015-06-03

申请号：EP12817380

申请日：2012-07-20

申请人： KYOCERA CORP

发明人： TSUJINO MAHIRO ,  MIYAHARA MANABU

IPC分类号： H01L23/04 ,  H01L23/00 ,  H01L23/057 ,  H01L23/10

CPC分类号： H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

公开(公告)号：EP4352786A1

公开(公告)日：2024-04-17

申请号：EP22731411.9

申请日：2022-05-24

申请人： Wolfspeed, Inc.

发明人： RICE, David ,  FISHER, Jeremy

IPC分类号： H01L23/66 ,  H03F1/56

CPC分类号： H01L23/66 ,  H01L2223/661120130101 ,  H01L2223/664420130101 ,  H01L2223/662720130101 ,  H01L2223/665520130101 ,  H01L2223/667220130101 ,  H01L24/42 ,  H03F1/565 ,  H01L2924/1910720130101 ,  H01L2924/1904120130101 ,  H01L2924/1910520130101 ,  H01L2924/1519220130101 ,  H01L2924/1901120130101 ,  H01L2224/4819520130101 ,  H01L2924/1904220130101 ,  H01L2924/1904320130101 ,  H01L24/32 ,  H01L2224/3224520130101 ,  H01L2224/7326520130101 ,  H01L2224/4917520130101 ,  H01L24/49 ,  H01L2224/4809120130101 ,  H01L2924/18120130101 ,  H01L24/48 ,  H01L2924/0001420130101 ,  H01L24/73 ,  H01L2924/1619520130101 ,  H03F3/195 ,  H03F1/0288 ,  H03F3/245

公开(公告)号：EP3297023A1

公开(公告)日：2018-03-21

申请号：EP17189912.3

申请日：2017-09-07

申请人： General Electric Company

发明人： GOWDA, Arun Virupaksha

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/34 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/42 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/00012

摘要： An integrated circuit (IC) device (300) is described. The IC device (300) includes a substrate (302). A connection component (304) including a cavity (324) therethrough is attached to the substrate (302). A memory die (312) is positioned in the cavity (324) of the connection component (304) and is electrically coupled to the substrate (302). A logic die (308) extends over the memory die (312) and at least a portion of the connection component (304), and is electrically coupled to the connection component (304) and the memory die (312). The connection component (304) is formed free of through silicon vias and is electrically coupled to the substrate (302) through wire bonding.

摘要翻译： 描述了集成电路（IC）器件（300）。 IC器件（300）包括衬底（302）。 包括穿过其中的空腔（324）的连接部件（304）附接到衬底（302）。 存储器管芯（312）位于连接部件（304）的空腔（324）中并电耦合至基板（302）。 逻辑管芯（308）在存储器管芯（312）和连接部件（304）的至少一部分上延伸，并电连接到连接部件（304）和存储器管芯（312）。 连接部件（304）形成为没有硅通孔并且通过引线键合电耦合到衬底（302）。

公开(公告)号：EP2731130A1

公开(公告)日：2014-05-14

申请号：EP12192281.9

申请日：2012-11-12

申请人： NXP B.V.

发明人： Weinschenk, Christian

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/315 ,  H01L24/42 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The invention refers to method for packaging an integrated circuit (IC) comprising steps of:
- attaching at least one die on a substrate;
- attaching bond-wires from the die(s) to package terminal pads;
- mold or dispense a thermo-degradable material on the substrate, die(s) and bond-wires;
- mold an encapsulant material;
- decompose the thermo-degradable materials by temperature treatment.

摘要翻译： 本发明涉及一种用于封装集成电路（IC）的方法，包括以下步骤： - 将至少一个管芯附着在衬底上; - 将粘合线从模具附接到封装端子焊盘; - 在基底，模具和接合线上模制或分配热可降解材料; - 模塑密封材料; - 通过温度处理分解热降解材料。

公开(公告)号：EP3387674A1

公开(公告)日：2018-10-17

申请号：EP16819775.4

申请日：2016-12-07

申请人： Microchip Technology Incorporated

发明人： DIX, Greg ,  YACH, Randy L. ,  MAZZILLI, Francesco

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L21/31105 ,  H01L21/52 ,  H01L23/3142 ,  H01L23/48 ,  H01L23/5222 ,  H01L23/5223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/42 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0652 ,  H01L28/00 ,  H01L28/40 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/14104 ,  H01L2224/1412 ,  H01L2224/16145 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/0665

摘要： The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.

公开(公告)号：EP3380267A1

公开(公告)日：2018-10-03

申请号：EP16781574.5

申请日：2016-09-16

申请人： Heraeus Materials Singapore Pte. Ltd. ,  Heraeus Oriental HiTec Co., Ltd.

发明人： KANG, Il Tae ,  TARK,Yong-Deok ,  CHO, Mong Hyun ,  KIM, Jong Su ,  JUNG, Hyun Seok ,  KIM, Tae Yeop ,  ZHANG, Xi ,  SARANGAPANI, Murali

IPC分类号： B23K35/30 ,  B23K35/02 ,  C22C5/06 ,  H01L23/00 ,  C23C28/00 ,  C23C30/00

CPC分类号： B23K35/3006 ,  B23K20/007 ,  B23K35/0227 ,  B23K35/0261 ,  B23K35/404 ,  C22C5/06 ,  C22C5/08 ,  C22F1/002 ,  C22F1/02 ,  C22F1/14 ,  C23C14/022 ,  C23C14/165 ,  C23C28/021 ,  C25D5/10 ,  C25D5/12 ,  C25D5/50 ,  C25D7/0607 ,  H01L24/42 ,  H01L24/43 ,  H01L24/44 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/43125 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/48511 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01078 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755

摘要： A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold.

公开(公告)号：EP3363047A1

公开(公告)日：2018-08-22

申请号：EP16856062.1

申请日：2016-10-12

申请人： Invensas Corporation

发明人： PRABHU, Ashok, S. ,  AWUJOOLA, Abiola ,  ZOHNI, Wael ,  SUBIDO, Willmar

IPC分类号： H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/552 ,  H01L24/01 ,  H01L24/42 ,  H01L24/44 ,  H01L24/45 ,  H01L24/46 ,  H01L24/47 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/42 ,  H01L2224/44 ,  H01L2224/45 ,  H01L2224/46 ,  H01L2224/47 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2224/49051 ,  H01L2224/49052 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2924/19107 ,  H01L2924/00014

摘要： Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

公开(公告)号：EP2738798A1

公开(公告)日：2014-06-04

申请号：EP12817380.4

申请日：2012-07-20

申请人： Kyocera Corporation

发明人： TSUJINO, Mahiro ,  MIYAHARA, Manabu

IPC分类号： H01L23/04

CPC分类号： H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device housing package(1) includes a base body (5) having, on its upper surface, a mounting region for placement of a semiconductor device (3); a frame body (7) having a frame-like portion disposed on the upper surface of the base body (5) so as to surround the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member (9) disposed in the opening so as to extend from an interior of the frame body (7) to an exterior thereof; wiring conductors (11) disposed on an upper surface of the insulating member (9) so as to extend from the interior of the frame body (7) to the exterior thereof; and a continuous metallic film (35) disposed on a part of the upper surface of the insulating member (9), the metallic film (35) lying outside the frame body (7) so as to surround the wiring conductors (11).