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公开(公告)号：JP2014049592A
公开(公告)日：2014-03-17
申请号：JP2012190993
申请日：2012-08-31
Applicant: Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
Inventor： SUGIYAMA MICHIAKI , KINOSHITA YOSHIHIRO
IPC: H01L25/18 , H01L25/065 , H01L25/07
CPC classification number: H01L21/50 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/6836 , H01L23/3128 , H01L23/49833 , H01L23/5283 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/27 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/0401 , H01L2224/04105 , H01L2224/05023 , H01L2224/05025 , H01L2224/05073 , H01L2224/05147 , H01L2224/0557 , H01L2224/05611 , H01L2224/05655 , H01L2224/12105 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/214 , H01L2224/215 , H01L2224/2731 , H01L2224/27334 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/81191 , H01L2224/81447 , H01L2224/81801 , H01L2224/82105 , H01L2224/82106 , H01L2224/83104 , H01L2224/83191 , H01L2224/83192 , H01L2224/83862 , H01L2224/92224 , H01L2224/92242 , H01L2224/92244 , H01L2224/94 , H01L2224/95 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06568 , H01L2225/06586 , H01L2924/00014 , H01L2924/12042 , H01L2924/13091 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/83 , H01L2924/00 , H01L2924/014 , H01L2924/01047 , H01L2224/27 , H01L2224/81 , H01L2924/01029 , H01L2224/19 , H01L2224/05552
Abstract: PROBLEM TO BE SOLVED: To prevent an excess stress from being applied to a connection part of two semiconductor chips in a semiconductor device in which a chip laminate including a small-diameter semiconductor chip and a large-diameter semiconductor chip is mounted on a top face of a base material.SOLUTION: In a semiconductor device manufacturing method, by mounting a large-diameter first semiconductor chip on a support substrate and subsequently mounting a small-diameter second semiconductor chip on the first semiconductor chip, since a tilt and slip of the second semiconductor chip mounted on the first semiconductor chip can be inhibited, an excess stress can be inhibited from being applied to a connection part of the first semiconductor chip and the second semiconductor chip.
Abstract translation: 要解决的问题：为了防止在将包括小直径半导体芯片和大直径半导体芯片的芯片层叠体安装在顶面上的半导体器件中的两个半导体芯片的连接部分上施加过量的应力 。在半导体器件制造方法中，通过将大直径第一半导体芯片安装在支撑基板上，随后将小直径第二半导体芯片安装在第一半导体芯片上，由于倾斜和滑动 可以抑制安装在第一半导体芯片上的第二半导体芯片，可以抑制过多的应力施加到第一半导体芯片和第二半导体芯片的连接部分。
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公开(公告)号：JP6092271B2
公开(公告)日：2017-03-08
申请号：JP2015012866
申请日：2015-01-27
Applicant: インテル コーポレイション
Inventor： トルステン メイヤー , ゲラルト オフナー , テオドーラ オシアンダー , フランク ツードック , クリスティアン ガイスラー
IPC: H01L21/768 , H01L23/522 , H01L23/12 , H01L21/3205
CPC classification number: H01L24/11 , H01L21/02282 , H01L21/02318 , H01L21/311 , H01L21/31111 , H01L21/31116 , H01L21/76802 , H01L21/76834 , H01L21/7685 , H01L21/76871 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/19 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0345 , H01L2224/03462 , H01L2224/0361 , H01L2224/0381 , H01L2224/03914 , H01L2224/0401 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/16227 , H01L2224/211 , H01L2224/8112 , H01L2224/81191 , H01L2224/81801 , H01L2224/821 , H01L2224/82105 , H01L2224/94 , H01L23/525 , H01L24/13 , H01L24/16 , H01L24/20 , H01L24/81 , H01L24/94 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/12042 , H01L2924/143 , H01L2924/181
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公开(公告)号：JP2013243175A
公开(公告)日：2013-12-05
申请号：JP2012113837
申请日：2012-05-17
Applicant: Shinko Electric Ind Co Ltd , 新光電気工業株式会社
Inventor： KUNIMOTO YUJI
CPC classification number: H01L23/49827 , H01L23/5383 , H01L23/5389 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/2402 , H01L2224/24105 , H01L2224/24265 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/82105 , H01L2224/92244 , H01L2224/97 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H05K1/0268 , H05K1/183 , H05K1/185 , H05K3/007 , H05K2201/10015 , H01L2224/82 , H01L2224/83 , H01L2924/00014 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a POP (Package On Package) structure which enables downsizing, and a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 10 comprises a semiconductor chip 60 and passive elements 40 which are embedded such that a part of the passive element is embedded and a part of the passive element projects from a first insulation layer 21. The passive element 40 includes an electrode 41 which is electrically connected with a wiring pattern 26 via via wiring 25y formed on an insulation layer 25. The semiconductor device 10 comprises first electrode pads 22 each electrically connected with another semiconductor device 70 via a bonding part 80. A projection amount of the passive element 40 from the first insulation layer 21 is less than a clearance between the first insulation layer 21 and an opposed surface of the other semiconductor device 70.
Abstract translation: 要解决的问题：提供一种具有能够实现小型化的POP（封装封装）结构的半导体器件和半导体器件的制造方法。半导体器件10包括半导体芯片60和嵌入的无源元件40 使得无源元件的一部分被嵌入，并且无源元件的一部分从第一绝缘层21突出。无源元件40包括电极41，其经由布线25y与布线图案26电连接，该布线图案形成在绝缘层 半导体器件10包括通过接合部分80与另一个半导体器件70电连接的第一电极焊盘22.来自第一绝缘层21的无源元件40的突出量小于第一绝缘层 21和另一个半导体器件70的相对表面。
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Patent Agency Ranking
公开(公告)号：JP6100489B2
公开(公告)日：2017-03-22
申请号：JP2012190993
申请日：2012-08-31
Applicant: ルネサスエレクトロニクス株式会社
IPC: H01L25/07 , H01L25/18 , H01L25/065
CPC classification number: H01L21/50 , H01L21/561 , H01L23/3128 , H01L24/14 , H01L24/19 , H01L24/20 , H01L24/92 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L21/56 , H01L21/563 , H01L21/6836 , H01L2221/68327 , H01L2224/0401 , H01L2224/04105 , H01L2224/05023 , H01L2224/05025 , H01L2224/05073 , H01L2224/05147 , H01L2224/0557 , H01L2224/05611 , H01L2224/05655 , H01L2224/12105 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/14131 , H01L2224/14135 , H01L2224/14136 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/17181 , H01L2224/214 , H01L2224/215 , H01L2224/2731 , H01L2224/27334 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73104 , H01L2224/73204 , H01L2224/73253 , H01L2224/73259 , H01L2224/81191 , H01L2224/81447 , H01L2224/81801 , H01L2224/82105 , H01L2224/82106 , H01L2224/83104 , H01L2224/83191 , H01L2224/83192 , H01L2224/83862 , H01L2224/92224 , H01L2224/92242 , H01L2224/92244 , H01L2224/94 , H01L2224/95 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06568 , H01L2225/06586 , H01L23/49833 , H01L23/5283 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/94 , H01L2924/00014 , H01L2924/12042 , H01L2924/13091 , H01L2924/15311 , H01L2924/15313 , H01L2924/181 , H01L2924/3511
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公开(公告)号：JP2015173256A
公开(公告)日：2015-10-01
申请号：JP2015012866
申请日：2015-01-27
Applicant: インテル コーポレイション
Inventor： トルステン メイヤー , ゲラルト オフナー , テオドーラ オシアンダー , フランク ツードック , クリスティアン ガイスラー
IPC: H01L21/768 , H01L23/522 , H01L23/12 , H01L21/3205
CPC classification number: H01L24/05 , H01L24/02 , H01L24/03 , H01L24/19 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0345 , H01L2224/03462 , H01L2224/0361 , H01L2224/0381 , H01L2224/03914 , H01L2224/0401 , H01L2224/05083 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/12105 , H01L2224/13022 , H01L2224/131 , H01L2224/16227 , H01L2224/211 , H01L2224/81191 , H01L2224/81801 , H01L2224/821 , H01L2224/82105 , H01L2224/94 , H01L23/525 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/20 , H01L24/81 , H01L24/94 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/12042 , H01L2924/143 , H01L2924/181
Abstract: 【課題】ICパッケージの製造コストを低減することに加えて、パッケージの接続部の整合性及び信頼性を高める集積回路パッケージの組み立て方法、ICパッケージ及びパッケージアセンブリを提供する。 【解決手段】本開示の実施形態は集積回路パッケージの組み立て方法に関する。本開示の実施形態では、当該方法は非パターン化パッシベーション層を有するウエハを提供して、該ウエハに埋め込まれた金属導体の腐食を防ぐ工程を含み得る。当該方法は、前記パッシベーション層の上に誘電体材料を積層して誘電体層を形成する工程及び前記誘電体材料を選択的に除去して、前記誘電体層に空隙を形成する工程をさらに含み得る。これらの空隙は前記金属導体の上に配置された前記パッシベーション層の一部を露出し得る。そして当該方法は、前記パッシベーション層の前記一部を除去して前記金属導体を露出する工程を含み得る。他の実施形態も説明及び/又は請求項に記載され得る。 【選択図】図1
Abstract translation: 要解决的问题：提供集成电路封装组装方法，IC封装和封装组件，其增加封装连接的可靠性和一致性，同时降低IC封装的制造成本。解决方案：本公开的实施例是针对 涉及组装集成电路封装的方法。 在本公开的实施例中，该方法可以包括提供具有未图案化钝化层的晶片，以防止嵌入晶片中的金属导体的腐蚀。 该方法还可以包括在绝缘层上层叠电介质材料以形成电介质层，并且选择性地去除电介质材料以在电介质层中形成空隙。 这些空隙可以露出设置在金属导体上的钝化层的部分。 该方法可以包括去除钝化层的部分以露出金属导体。 可以描述和/或要求保护其他实施例。
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公开(公告)号：JP6124513B2
公开(公告)日：2017-05-10
申请号：JP2012113837
申请日：2012-05-17
Applicant: 新光電気工業株式会社
Inventor： 国本 裕治
CPC classification number: H01L23/49827 , H01L23/5383 , H01L23/5389 , H01L24/24 , H01L24/97 , H05K1/183 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/2402 , H01L2224/24105 , H01L2224/24265 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/82105 , H01L2224/92244 , H01L2224/97 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/92 , H01L25/0657 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H05K1/0268 , H05K1/185 , H05K2201/10015 , H05K3/007
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公开(公告)号：JP5926547B2
公开(公告)日：2016-05-25
申请号：JP2011266379
申请日：2011-12-06
Applicant: ゼネラル・エレクトリック・カンパニイ
Inventor： リチャード・アルフレッド・ビュープレ , パウル・アラン・マッコンネリー , アルン・ビルパクシャ・ゴウワダ , トマス・バート・ゴルチカ
CPC classification number: H01L23/3171 , H01L21/56 , H01L23/3164 , H01L23/3192 , H01L24/19 , H01L24/20 , H01L29/0657 , H01L2224/24 , H01L2224/24011 , H01L2224/2402 , H01L2224/24227 , H01L2224/76155 , H01L2224/82 , H01L2224/82102 , H01L2224/82105 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/12036 , H01L2924/1204 , H01L2924/12042 , H01L2924/12043
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公开(公告)号：JP2012124486A
公开(公告)日：2012-06-28
申请号：JP2011266379
申请日：2011-12-06
Applicant: General Electric Co
, ゼネラル・エレクトリック・カンパニイ Inventor： BEAUPRE RICHARD ALFRED , PAUL ALLEN MACONELLY , ARUN VIRUPAKSHA GOWDA , THOMAS BART GORCHICA
CPC classification number: H01L23/3171 , H01L21/56 , H01L23/3164 , H01L23/3192 , H01L24/19 , H01L24/20 , H01L29/0657 , H01L2224/24 , H01L2224/24011 , H01L2224/2402 , H01L2224/24227 , H01L2224/76155 , H01L2224/82 , H01L2224/82102 , H01L2224/82105 , H01L2224/92144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/12036 , H01L2924/1204 , H01L2924/12042 , H01L2924/12043 , H01L2924/00
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device package having a high breakdown voltage and low parasitic inductance.SOLUTION: A first passivation layer 22 is applied on a semiconductor device 12 and a base dielectric laminate 42, which has a thickness greater than that of the first passivation layer, is affixed to a first surface 18 of the semiconductor device. A second passivation layer 30 having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover a second surface 20 and edges 24 of the semiconductor device, and metal interconnects are coupled to connection pads, with the metal interconnects extending through vias 34 formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
Abstract translation: 要解决的问题：提供具有高击穿电压和低寄生电感的半导体器件封装。 解决方案：第一钝化层22施加在半导体器件12上，并且具有大于第一钝化层的厚度的基底电介质层压体42固定到半导体器件的第一表面18。 具有大于第一钝化层的厚度的第二钝化层30施加在第一钝化层和半导体器件上以覆盖半导体器件的第二表面20和边缘24，并且金属互连件连接到连接焊盘， 其中金属互连件延伸穿过通过第一和第二钝化层形成的通孔34和基底电介质层压片，以形成与连接焊盘的连接。 版权所有（C）2012，JPO＆INPIT
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