公开(公告)号：US08798291B2

公开(公告)日：2014-08-05

申请号：US12233919

申请日：2008-09-19

Applicant: Bang-Chiang Lan ,  Ming-I Wang ,  Li-Hsun Ho ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang

Inventor： Bang-Chiang Lan ,  Ming-I Wang ,  Li-Hsun Ho ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang

IPC: H04R31/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  H04R3/00 ,  H04R7/00 ,  H04R19/005 ,  H04R31/00 ,  H04R2499/11 ,  Y10T29/49002

Abstract: A structure of a micro-electro-mechanical systems (MEMS) electroacoustic transducer includes a substrate, a diaphragm, a silicon material layer, and a conductive pattern. The substrate includes an MEMS device region. The diaphragm has openings, and is disposed in the MEMS device region. A first cavity is formed between the diaphragm and the substrate. The silicon material layer is disposed on the diaphragm and seals the diaphragm. The conductive pattern is disposed beneath the diaphragm in the MEMS device region.

Abstract translation: 微电子机械系统（MEMS）电声换能器的结构包括基板，隔膜，硅材料层和导电图案。 衬底包括MEMS器件区域。 隔膜具有开口，并且设置在MEMS器件区域中。 在隔膜和基板之间形成第一空腔。 硅材料层设置在隔膜上并密封隔膜。 导电图案设置在MEMS器件区域中的隔膜下方。

公开(公告)号：US08642986B2

公开(公告)日：2014-02-04

申请号：US12565154

申请日：2009-09-23

Applicant: Tzung-Han Tan ,  Bang-Chiang Lan ,  Ming-I Wang ,  Tzung-I Su ,  Chien-Hsin Huang ,  Hui-Min Wu ,  Chao-An Su ,  Min Chen ,  Meng-Jia Lin

Inventor： Tzung-Han Tan ,  Bang-Chiang Lan ,  Ming-I Wang ,  Tzung-I Su ,  Chien-Hsin Huang ,  Hui-Min Wu ,  Chao-An Su ,  Min Chen ,  Meng-Jia Lin

IPC: H01L29/84 ,  H01L21/30

CPC classification number: B81C1/00238

Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.

Abstract translation: 提供了一种其中埋有微机电系统（MEMS）器件的集成电路（IC）。 集成电路包括衬底，金属氧化物半导体（MOS）器件，金属互连和MEMS器件。 衬底具有逻辑电路区域和MEMS区域。 MOS器件位于衬底的逻辑电路区域上。 由多层电线形成的金属互连和多个通孔位于衬底上方以连接MOS器件。 MEMS器件位于MEMS区域上，并且包括位于金属互连中的任何两个相邻电平线之间并连接到金属互连的夹层膜。

公开(公告)号：US08502382B2

公开(公告)日：2013-08-06

申请号：US13459268

申请日：2012-04-30

Applicant: Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Li-Che Chen ,  Meng-Jia Lin

Inventor： Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Li-Che Chen ,  Meng-Jia Lin

IPC: H01L23/48

CPC classification number: H01L24/02 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/115 ,  B81C1/00246 ,  B81C2203/0714 ,  H01L23/585 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which encompasses the connection region. The protection structure includes at least a barrier, an insulation layer and a mask layer. The barrier is disposed in the dielectric layer in the peripheral region. The insulation layer is disposed on the dielectric layer. The mask layer is disposed on the dielectric layer and covers the insulation layer and the mask layer includes an opening to expose the connection region of the pad.

Abstract translation: 提供垫的保护结构。 衬垫设置在半导体衬底上的电介质层中，衬垫包括连接区域和包围连接区域的周边区域。 保护结构至少包括屏障，绝缘层和掩模层。 阻挡层设置在周边区域的电介质层中。 绝缘层设置在电介质层上。 掩模层设置在电介质层上并覆盖绝缘层，掩模层包括露出焊盘连接区域的开口。

公开(公告)号：US20130093104A1

公开(公告)日：2013-04-18

申请号：US13272289

申请日：2011-10-13

Applicant: Hui-Min WU ,  Ming-I Wang ,  Kuan-Yu Wang ,  Kun-Che Hsieh ,  Chien-Hsin Huang

Inventor： Hui-Min WU ,  Ming-I Wang ,  Kuan-Yu Wang ,  Kun-Che Hsieh ,  Chien-Hsin Huang

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/3192 ,  B81B7/0006 ,  B81B2207/015 ,  H01L23/291 ,  H01L23/293 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A bond pad structure comprises an interconnection structure and an isolation layer. The dielectric layer has an opening and a metal pad. The isolation layer is disposed on the interconnection structure and extends into the opening until it is in contact with the metal pad, whereby the sidewalls of the opening is blanketed by the isolation layer, and a portion of the metal pad is exposed from the opening.

Abstract translation: 接合焊盘结构包括互连结构和隔离层。 电介质层具有开口和金属垫。 隔离层设置在互连结构上并延伸到开口中直到与金属垫接触，由此隔离层覆盖开口的侧壁，并且金属垫的一部分从开口露出。

公开(公告)号：US08310065B2

公开(公告)日：2012-11-13

申请号：US12985344

申请日：2011-01-06

Applicant: Hui-Min Wu ,  Bang-Chiang Lan ,  Chien-Hsin Huang ,  Kuan-Yu Wang ,  Chao-An Su ,  Tzung-I Su

Inventor： Hui-Min Wu ,  Bang-Chiang Lan ,  Chien-Hsin Huang ,  Kuan-Yu Wang ,  Chao-An Su ,  Tzung-I Su

IPC: H01L23/48

CPC classification number: B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0735 ,  H01L21/76829 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a wafer structure includes: providing a substrate having a plurality of die regions and an edge region surrounding the die regions defined thereon; then, forming a dielectric layer, a plurality of MEMS devices, a plurality of metal-interconnect structures and a plurality bonding pads on the substrate in the die regions; next, removing the dielectric layer disposed on the substrate of the edge region to expose the substrate; and thereafter, forming a passivation layer to cover the substrate and the dielectric layer.

Abstract translation: 晶片结构的制造方法包括：提供具有多个管芯区域的衬底和围绕限定在其上的管芯区域的边缘区域; 然后在所述管芯区域中的所述衬底上形成电介质层，多个MEMS器件，多个金属互连结构和多个接合焊盘; 接下来，去除设置在边缘区域的基板上的电介质层，以露出基板; 然后形成钝化层以覆盖基板和电介质层。

公开(公告)号：US08299555B2

公开(公告)日：2012-10-30

申请号：US12618774

申请日：2009-11-15

Applicant: Tzung-I Su ,  Chao-An Su ,  Ming-I Wang ,  Bang-Chiang Lan ,  Tzung-Han Tan ,  Hui-Min Wu ,  Chien-Hsin Huang ,  Min Chen ,  Meng-Jia Lin

Inventor： Tzung-I Su ,  Chao-An Su ,  Ming-I Wang ,  Bang-Chiang Lan ,  Tzung-Han Tan ,  Hui-Min Wu ,  Chien-Hsin Huang ,  Min Chen ,  Meng-Jia Lin

IPC: H01L31/0232

CPC classification number: G02B6/1228 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/136 ,  G02B6/428

Abstract: A method of fabricating a semiconductor optoelectronic structure is provided. First, a substrate is provided, and a waveguide is formed therein, and then a plurality of dielectric layers is formed on the waveguide. Next, a contact pad and a passivation layer are provided on the dielectric layers and a patterned mask layer is formed thereon. Last, an etching process is provided by using the patterned mask layer to expose the contact pad and remove a portion of the passivation layer and the dielectric layers to form a transformer.

Abstract translation: 提供一种制造半导体光电子结构的方法。 首先，提供基板，并且在其中形成波导，然后在波导上形成多个电介质层。 接下来，在电介质层上设置接触焊盘和钝化层，并且在其上形成图案化的掩模层。 最后，通过使用图案化掩模层来暴露接触焊盘并去除钝化层和电介质层的一部分以形成变压器来提供蚀刻工艺。

公开(公告)号：US08096048B2

公开(公告)日：2012-01-17

申请号：US12849168

申请日：2010-08-03

Applicant: Bang-Chiang Lan ,  Ming-I Wang ,  Li-Hsun Ho ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang ,  Tzung-I Su

Inventor： Bang-Chiang Lan ,  Ming-I Wang ,  Li-Hsun Ho ,  Hui-Min Wu ,  Min Chen ,  Chien-Hsin Huang ,  Tzung-I Su

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81C2203/0714 ,  B81C2203/0742 ,  Y10T29/41 ,  Y10T29/49155

Abstract: A method for fabricating a MEMS is described as follows. A substrate is provided, including a circuit region and a MEMS region separated from each other. A first metal interconnection structure is formed on the substrate in the circuit region, and simultaneously a first dielectric structure is formed on the substrate in the MEMS region. A second metal interconnection structure is formed on the first metal interconnection structure, and simultaneously a second dielectric structure, at least two metal layers and at least one protection ring are formed on the first dielectric structure. The metal layers and the protection ring are formed in the second dielectric structure and the protection ring connects two adjacent metal layers to define an enclosed space between two adjacent metal layers. The first dielectric structure and the second dielectric structure outside the enclosed space are removed to form a MEMS device in the MEMS region.

Abstract translation: MEMS的制造方法如下所述。 提供了包括彼此分离的电路区域和MEMS区域的衬底。 第一金属互连结构形成在电路区域中的衬底上，并且同时在MEMS区域中的衬底上形成第一电介质结构。 第二金属互连结构形成在第一金属互连结构上，并且同时具有第二电介质结构，至少两个金属层和至少一个保护环形成在第一电介质结构上。 金属层和保护环形成在第二电介质结构中，并且保护环连接两个相邻的金属层以限定两个相邻金属层之间的封闭空间。 去除封闭空间外部的第一电介质结构和第二电介质结构，以在MEMS区域中形成MEMS器件。

公开(公告)号：US20110084394A1

公开(公告)日：2011-04-14

申请号：US12577734

申请日：2009-10-13

Applicant: Hui-Min Wu ,  Bang-Chiang Lan ,  Ming-I Wang ,  Tzung-I Su ,  Chien-Hsin Huang ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

Inventor： Hui-Min Wu ,  Bang-Chiang Lan ,  Ming-I Wang ,  Tzung-I Su ,  Chien-Hsin Huang ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

IPC: H01L23/485

CPC classification number: H01L24/05 ,  B81B7/0006 ,  B81B2207/015 ,  B81C2203/0714 ,  H01L23/562 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.

Abstract translation: 提供半导体结构。 半导体结构包括衬底，电介质层，衬垫结构和保护结构。 电介质层设置在基板上。 焊盘结构设置在电介质层中。 垫结构包括多个第一金属层和多个彼此垂直电连接的插塞。 在衬垫结构和衬底之间没有设置接触插头。 保护结构设置在电介质层中并且包围衬垫结构。

公开(公告)号：US20110084344A1

公开(公告)日：2011-04-14

申请号：US12579395

申请日：2009-10-14

Applicant: Chien-Hsin Huang ,  Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

Inventor： Chien-Hsin Huang ,  Bang-Chiang Lan ,  Ming-I Wang ,  Hui-Min Wu ,  Tzung-I Su ,  Chao-An Su ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin

IPC: H01L29/84 ,  H01L21/30

CPC classification number: B81C1/00801 ,  B81B2201/0257 ,  B81B2207/015 ,  B81C2201/014 ,  B81C2203/0735

Abstract: A method of fabricating MEMS device includes: providing a substrate with a first surface and a second surface. The substrate includes at least one logic region and at least one MEMS region. The logic region includes at least one logic device positioned on the first surface of the substrate. Then, an interlayer material is formed on the first surface of the substrate within the MEMS region. Finally, the second surface of the substrate within the MEMS region is patterned. After the pattern process, a vent pattern is formed in the second surface of the substrate within the MEMS region. The interlayer material does not react with halogen radicals. Therefore, during the formation of the vent pattern, the substrate is protected by the interlayer material and the substrate can be prevented from forming any undercut.

Abstract translation: 一种制造MEMS器件的方法包括：向基片提供第一表面和第二表面。 衬底包括至少一个逻辑区域和至少一个MEMS区域。 逻辑区域包括位于衬底的第一表面上的至少一个逻辑器件。 然后，在MEMS区域内的衬底的第一表面上形成中间层材料。 最后，对MEMS区域内的衬底的第二表面进行图案化。 在图案处理之后，在MEMS区域内的衬底的第二表面中形成通气图案。 中间层材料不与卤素原子反应。 因此，在形成通气图案的过程中，基板被中间层材料保护，并且可以防止基板形成任何底切。

公开(公告)号：US20110037133A1

公开(公告)日：2011-02-17

申请号：US12542671

申请日：2009-08-17

Applicant: Tzung-I Su ,  Bang-Chiang Lan ,  Chao-An Su ,  Hui-Min Wu ,  Ming-I Wang ,  Chien-Hsin Huang ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin ,  Wen-Yu Su

Inventor： Tzung-I Su ,  Bang-Chiang Lan ,  Chao-An Su ,  Hui-Min Wu ,  Ming-I Wang ,  Chien-Hsin Huang ,  Tzung-Han Tan ,  Min Chen ,  Meng-Jia Lin ,  Wen-Yu Su

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/08

CPC classification number: H01L31/035281 ,  H01L27/1461 ,  H01L31/105 ,  H01L31/1804 ,  H01L31/1808 ,  Y02E10/547 ,  Y02P70/521

Abstract: A semiconductor photodetector structure is provided. The structure includes a substrate, a photodetecting element and a semiconductor layer disposed on the photodetecting element. The substrate includes a first semiconductor material and includes a deep trench. The surface of the deep trench includes a first type dopant. The photodetecting element is disposed in the deep trench. The photodetecting element includes a second semiconductor material. The semiconductor layer includes a second type dopant.

Abstract translation: 提供半导体光电检测器结构。 该结构包括基板，受光元件和设置在光电检测元件上的半导体层。 衬底包括第一半导体材料并且包括深沟槽。 深沟槽的表面包括第一类型的掺杂剂。 光检测元件设置在深沟槽中。 光检测元件包括第二半导体材料。 半导体层包括第二种掺杂剂。