公开(公告)号：US20180261573A1

公开(公告)日：2018-09-13

申请号：US15454520

申请日：2017-03-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/24 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/24 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586

Abstract: A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

公开(公告)号：US20180151478A1

公开(公告)日：2018-05-31

申请号：US15364139

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/4889 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/492 ,  H01L23/49527 ,  H01L23/552 ,  H01L24/48 ,  H01L2224/4901 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/85

Abstract: A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and electrically connected to the electronic device, and the conductive frame includes a plurality of leads. The first molding layer covers the electronic device and a portion of the conductive frame, and is disposed between at least two adjacent ones of the leads.

公开(公告)号：US20240213168A1

公开(公告)日：2024-06-27

申请号：US18434711

申请日：2024-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming WANG ,  Tien-Szu CHEN ,  Wen-Chih SHEN ,  Hsing-Wen LEE ,  Hsiang-Ming FENG

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L25/065 ,  H01P3/06

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/66 ,  H01P3/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US20180374811A1

公开(公告)日：2018-12-27

申请号：US15630843

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chung-Chieh YANG ,  Sheng-Ming WANG ,  Tien-Szu CHEN

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19107 ,  H01L2924/30101 ,  H01L2924/351

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and including a power layer adjacent to the first surface of the carrier, an electrical component disposed on the first surface of the carrier, and a conductive element disposed on the first surface of the carrier. The electrical component is electrically connected to the power layer. The conductive element is electrically connected to the power layer. The conductive element, the power layer, and the electrical component form a power-transmission path.

公开(公告)号：US20180350626A1

公开(公告)日：2018-12-06

申请号：US16102527

申请日：2018-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Yu-Tzu PENG

IPC: H01L21/48 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

公开(公告)号：US20180233457A1

公开(公告)日：2018-08-16

申请号：US15430355

申请日：2017-02-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  I-Cheng WANG ,  Wun-Jheng SYU ,  Yu-Tzu PENG

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/367 ,  H01L23/29 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2225/1094

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

公开(公告)号：US20160225708A1

公开(公告)日：2016-08-04

申请号：US15006306

申请日：2016-01-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Chun-Che LEE ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/288 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.

Abstract translation: 半导体衬底包括绝缘层和埋在绝缘层的表面上的导电电路层。 导电电路层包括第一部分和第二部分。 第一部分包括接合焊盘和导电迹线的一部分，并且第二部分包括导电迹线的另一部分。 第一部分的上表面不与第二部分的上表面共面。 半导体封装结构包括半导体衬底。

公开(公告)号：US20150318235A1

公开(公告)日：2015-11-05

申请号：US14704769

申请日：2015-05-05

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu CHEN ,  Sheng-Ming WANG ,  Kuang-Hsiung CHEN ,  Yu-Ying LEE

IPC: H01L23/498 ,  H01L23/495 ,  H01L21/77

CPC classification number: H01L23/49816 ,  H01L21/4828 ,  H01L23/49503 ,  H01L23/49534 ,  H01L23/49582 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49861 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.

Abstract translation: 提供了基板，其半导体封装件及其制造方法。 衬底包括上电路层和下电路层，上电路层包括至少一个迹线和至少一个焊盘，下电路层包括至少一个迹线和至少一个焊盘，其中上电路的迹线 层和下层电路层的迹线不对齐。

公开(公告)号：US20220359361A1

公开(公告)日：2022-11-10

申请号：US17873085

申请日：2022-07-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Che LEE ,  Ming-Chiang LEE ,  Yuan-Chang SU ,  Tien-Szu CHEN ,  Chih-Cheng LEE ,  You-Lung YEN

IPC: H01L23/498 ,  H05K1/11 ,  H05K3/00 ,  H01L21/48

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

公开(公告)号：US20210091006A1

公开(公告)日：2021-03-25

申请号：US17109111

申请日：2020-12-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming WANG ,  Tien-Szu CHEN ,  Wen-Chih SHEN ,  Hsing-Wen LEE ,  Hsiang-Ming FENG

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.